Table 5-1 SPI Interface Timing Requirements

5.5.1 Chip Status Byte

When the header byte, data byte, or command strobe is sent on the SPI interface, the chip status byte is sent by the CC 113L113L113L on the SO pin. The status byte contains key status signals, useful for the MCU. The first bit, s7, is the CHIP_RDYn signal and this signal must go low before the first positive edge of SCLK. The CHIP_RDYn signal indicates that the crystal is running.

Bits 6, 5, and 4 comprise the STATE value. This value reflects the state of the chip. The XOSC and power to the digital core are on in the IDLE state, but all other modules are in power down. The frequency and channel configuration should only be updated when the chip is in this state.

The last four bits (3:0) in the status byte contains FIFO_BYTES_AVAILABLE. For these bits to give any valid information, the R/W bit in the header byte must be set to 1. The FIFO_BYTES_AVAILABLE field will then contain the number of bytes that can be read from the RX FIFO. When FIFO_BYTES_AVAILABLE=15, 15 or more bytes can be read. The RX FIFO should not be emptied before the complete packet has been received (see the CC113L Errata Notes SWRZ038 for more details).

Table 5-2 gives a status byte summary.

5.5.2 Register Access

The configuration registers on the CC113L are located on SPI addresses from 0x00 to 0x2E. Table 5-17 lists all configuration registers. It is highly recommended to use SmartRF Studio SWRC176 to generate optimum register settings. The detailed description of each register is found in Section 5.21.1 and Section 5.21.2. All configuration registers can be both written to and read. The R/W bit controls if the register should be written to or read. When writing to registers, the status byte is sent on the SO pin each time a header byte or data byte is transmitted on the SI pin. When reading from registers, the status byte is sent on the SO pin each time a header byte is transmitted on the SI pin.

Registers with consecutive addresses can be accessed in an efficient way by setting the burst bit (B) in the header byte. The address bits (A₅ – A₀) set the start address in an internal address counter. This counter is incremented by one each new byte (every 8 clock pulses). The burst access is either a read or a write access and must be terminated by setting CSn high.

For register addresses in the range 0x30 – 0x3D, the burst bit is used to select between status registers when burst bit is one, and command strobes when burst bit is zero (see Section 5.5.3). Because of this, burst access is not available for status registers and they must be accessed one at a time. The status registers can only be read.

5.5.3 SPI Read

When reading register fields over the SPI interface while the register fields are updated by the radio hardware (that is, MARCSTATE or RXBYTES), there is a small, but finite, probability that a single read from the register is being corrupt. As an example, the probability of any single read from RXBYTES being corrupt, assuming the maximum data rate is used, is approximately 80 ppm. Refer to the CC113L Errata Notes SWRZ038 for more details.

5.5.4 Command Strobes

Command Strobes may be viewed as single byte instructions to CC113L. By addressing a command strobe register, internal sequences will be started. These commands are used to disable the crystal oscillator, enable receive mode, enable calibration etc. The 8 command strobes are listed in Table 5-16.

The command strobe registers are accessed by transferring a single header byte (no data is being transferred). That is, only the R/W bit, the burst access bit (set to 0), and the six address bits (in the range 0x30 through 0x3D) are written. The R/W bit can be either one or zero and will determine how the FIFO_BYTES_AVAILABLE field in the status byte should be interpreted.

When writing command strobes, the status byte is sent on the SO pin.

A command strobe may be followed by any other SPI access without pulling CSn high. However, if an SRES strobe is being issued, one will have to wait for SO to go low again before the next header byte can be issued as shown in Figure 5-4. The command strobes are executed immediately, with the exception of the SPWD and the SXOFF strobes, which are executed when CSn goes high.

Figure 5-4 SRES Command Strobe

5.5.5 RX FIFO Access

The 64-byte RX FIFO is accessed through the 0x3F address. The RX FIFO is write-only and the R/W bit should therefore be one.

The burst bit is used to determine if the RX FIFO access is a single byte access or a burst access. The single byte access method expects a header byte with the burst bit set to zero and one data byte. After the data byte, a new header byte is expected; hence, CSn can remain low. The burst access method expects one header byte and then consecutive data bytes until terminating the access by setting CSn high.

The following header bytes access the RX FIFO:

• 0xBF: Single byte access to RX FIFO
• 0xFF: Burst access to RX FIFO

The RX FIFO may be flushed by issuing a SFRX command strobe. A SFRX command strobe can only be issued in the IDLE, or RXFIFO_OVERFLOW states. The RX FIFO is flushed when going to the SLEEP state.

Figure 5-5 gives a brief overview of different register access types possible.

Figure 5-5 Register Access Types

5.6.1 Configuration Interface

The microcontroller uses four I/O pins for the SPI configuration interface (SI, SO, SCLK, and CSn). The SPI is described in Section 5.5.

5.6.2 General Control and Status Pins

The CC113L has two dedicated configurable pins (GDO0 and GDO2) and one shared pin (GDO1) that can output internal status information useful for control software. These pins can be used to generate interrupts on the MCU. See Section 5.18 for more details on the signals that can be programmed.

GDO1 is shared with the SO pin in the SPI interface. The default setting for GDO1/SO is 3-state output. By selecting any other of the programming options, the GDO1/SO pin will become a generic pin. When CSn is low, the pin will always function as a normal SO pin.

Table 5-3 Data Rate Step Size (Assuming a 26-MHz crystal)

Table 5-4 Channel Filter Bandwidths [kHz] (Assuming a 26-MHz Crystal)

5.9.1 Frequency Offset Compensation

The CC113L has a very fine frequency resolution (see Section 4.8). This feature can be used to compensate for frequency offset and drift.

When using 2-FSK, GFSK, or 4-FSK modulation, the demodulator will compensate for the offset between the transmitter and receiver frequency within certain limits, by estimating the center of the received data. The frequency offset compensation configuration is controlled from the FOCCFG register. By compensating for a large frequency offset between the transmitter and the receiver, the sensitivity can be improved, see DN005 SWRA122.

The tracking range of the algorithm is selectable as fractions of the channel bandwidth with the FOCCFG.FOC_LIMIT configuration register.

If the FOCCFG.FOC_BS_CS_GATE bit is set, the offset compensator will freeze until carrier sense asserts. This may be useful when the radio is in RX for long periods with no traffic, since the algorithm may drift to the boundaries when trying to track noise.

The tracking loop has two gain factors, which affects the settling time and noise sensitivity of the algorithm. FOCCFG.FOC_PRE_K sets the gain before the sync word is detected, and FOCCFG.FOC_POST_K selects the gain after the sync word has been found.

The estimated frequency offset value is available in the FREQEST status register. This can be used for permanent frequency offset compensation. By writing the value from FREQEST into FSCTRL0.FREQOFF, the frequency synthesizer will automatically be adjusted according to the estimated frequency offset. More details regarding this permanent frequency compensation algorithm can be found in DN015 SWRA159.

5.9.2 Bit Synchronization

The bit synchronization algorithm extracts the clock from the incoming symbols. The algorithm requires that the expected data rate is programmed as described in Section 5.7. Re-synchronization is performed continuously to adjust for error in the incoming symbol rate.

5.9.3 Byte Synchronization

Byte synchronization is achieved by a continuous sync word search. The sync word is a 16 bit configurable field (can be repeated to get a 32 bit) that must be inserted at the start of the packet by the transmitter (for example the CC115L, CC110L, or CC1101). The MSB in the sync word must be transmitted first. The demodulator uses this field to find the byte boundaries in the stream of bits. The sync word will also function as a system identifier, since only packets with the correct predefined sync word will be received if the sync word detection in RX is enabled in register MDMCFG2 (see Section 5.12.1). The sync word detector correlates against the user-configured 16 or 32 bit sync word. The correlation threshold can be set to 15/16, 16/16, or 30/32 bits match. The sync word can be further qualified using the preamble quality indicator mechanism described below and/or a carrier sense condition. The sync word is configured through the SYNC1 and SYNC0 registers.

Table 5-5 Received Packet Status Byte 1 (First Byte Appended After the Data)

Table 5-6 Received Packet Status Byte 2 (Second Byte Appended After the Data)

5.10.1 Packet Format

The format of the data packet can be configured and consists of the following items (see Figure 5-6):

• Preamble
• Synchronization word
• Optional length byte
• Optional address byte
• Payload
• Optional 2 byte CRC

Figure 5-6 Packet Format

The preamble pattern is an alternating sequence of ones and zeros that the receiver uses for bit synchronisation.

The synchronization word is a two-byte value set in the SYNC1 and SYNC0 registers. The sync word provides byte synchronization of the incoming packet. A one-byte sync word can be emulated by setting the SYNC1 value to the preamble pattern. It is also possible to emulate a 32 bit sync word by setting MDMCFG2.SYNC_MODE to 3 or 7. The sync word will then be repeated twice.

CC113L supports both constant packet length protocols and variable length protocols. Variable or fixed packet length mode can be used for packets up to 255 bytes. For longer packets, infinite packet length mode must be used.

Fixed packet length mode is selected by setting PKTCTRL0.LENGTH_CONFIG=0. The desired packet length is set by the PKTLEN register. This value must be different from 0.

In variable packet length mode, PKTCTRL0.LENGTH_CONFIG=1, the packet length is configured by the first byte after the sync word. The packet length is defined as the payload data, excluding the length byte and the optional CRC. The PKTLEN register is used to set the maximum packet length allowed in RX. Any packet received with a length byte with a value greater than PKTLEN will be discarded. The PKTLEN value must be different from 0.

With PKTCTRL0.LENGTH_CONFIG=2, the packet length is set to infinite and transmission and reception will continue until turned off manually. As described in Section 5.10.1.1, this can be used to support packet formats with different length configuration than natively supported by CC113L.

5.10.1.2 Packet Length > 255

The packet automation control register, PKTCTRL0, can be reprogrammed during RX. This opens the possibility to receive packets that are longer than 256 bytes and still be able to use the packet handling hardware support. At the start of the packet, the infinite packet length mode (PKTCTRL0.LENGTH_CONFIG=2) must be active. When receiving, the MCU reads out enough bytes to interpret the length field in the packet and sets the PKTLEN register to mod(length, 256). When less than 256 bytes remains of the packet, the MCU disables infinite packet length mode and activates fixed packet length mode (PKTCTRL0.LENGTH_CONFIG=0). When the internal byte counter reaches the PKTLEN value, the transmission or reception ends (the radio enters the state determined by RXOFF_MODE). Automatic CRC appending/checking can also be used (by setting PKTCTRL0.CRC_EN=1).

When for example a 600-byte packet is to be received, the MCU should do the following (see
Figure 5-7).

• Set PKTCTRL0.LENGTH_CONFIG=2.
• Receive enough bytes to interpret the length field
• Program the PKTLEN register to mod(600, 256) = 88.
• Receive at least 345 bytes (600 - 255)
• Set PKTCTRL0.LENGTH_CONFIG=0.
• The reception ends when the packet counter reaches 88. A total of 600 bytes have been received.

Figure 5-7 Packet Length > 255

5.10.2 Packet Filtering

CC113L supports three different types of packet-filtering; address filtering, maximum length filtering, and CRC filtering.

5.10.3 Packet Handling in Receive Mode

In receive mode, the demodulator and packet handler will search for a valid preamble and the sync word. When found, the demodulator has obtained both bit and byte synchronization and will receive the first payload byte.

When variable packet length mode is enabled, the first byte is the length byte. The packet handler stores this value as the packet length and receives the number of bytes indicated by the length byte. If fixed packet length mode is used, the packet handler will accept the programmed number of bytes.

Next, the packet handler optionally checks the address and only continues the reception if the address matches. If automatic CRC check is enabled, the packet handler computes CRC and matches it with the appended CRC checksum.

At the end of the payload, the packet handler will optionally write two extra packet status bytes (see Table 5-5 and Table 5-6) that contain CRC status, link quality indication, and RSSI value.

5.10.4 Packet Handling in Firmware

When implementing a packet oriented radio protocol in firmware, the MCU needs to know when a packet has been received. Additionally, for packets longer than 64 bytes, the RX FIFO needs to be read while in RX. There are two possible solutions to get the necessary status information:

a. Interrupt Driven Solution

The GDO pins can be used to give an interrupt when a sync word has been received or when a complete packet has been received by setting IOCFGx.GDOx_CFG=0x06. In addition, there are two configurations for the IOCFGx.GDOx_CFG register that can be used as an interrupt source to provide information on how many bytes that are in the RX FIFO (IOCFGx.GDOx_CFG=0x00 and IOCFGx.GDOx_CFG=0x01). See Table 5-15 for more information.

b. SPI Polling

The PKTSTATUS register can be polled at a given rate to get information about the current GDO2 and GDO0 values respectively. The RXBYTES register can be polled at a given rate to get information about the number of bytes in the RX FIFO. Alternatively, the number of bytes in the RX FIFO can be read from the chip status byte returned on the MISO line each time a header byte, data byte, or command strobe is sent on the SPI bus.

It is recommended to employ an interrupt driven solution since high rate SPI polling reduces the RX sensitivity. Furthermore, as explained in Section 5.5.3 and the CC113L Errata Notes SWRZ038, when using SPI polling, there is a small, but finite, probability that a single read from registers PKTSTATUS, and RXBYTES is being corrupt. The same is the case when reading the chip status byte.

5.11.1 Frequency Shift Keying

CC113L supports 2-(G)FSK and 4-FSK modulation. When selecting 4-FSK, the preamble and sync word to be received needs to be 2-FSK (see Figure 5-8).

When 2-FSK/GFSK/4-FSK modulation is used, the DEVIATN register specifies the expected frequency deviation of incoming signals in RX and should be the same as the deviation of the transmitted signal for demodulation to be performed reliably and robustly.

The frequency deviation is programmed with the DEVIATION_M and DEVIATION_E values in the DEVIATN register. The value has an exponent/mantissa form, and the resultant deviation is given by:

Equation 5.

The symbol encoding is shown in Table 5-7.

Figure 5-8 Data Sent Over the Air (MDMCFG2.MOD_FORMAT=100)

5.11.2 Amplitude Modulation

The amplitude modulation supported by CC113L is On-Off Keying (OOK).

OOK modulation simply turns the PA on or off to modulate ones and zeros respectively.

When using OOK, the AGC settings from the SmartRF Studio SWRC176 preferred FSK settings are not optimum. DN022 SWRA215 gives guidelines on how to find optimum OOK settings from the preferred settings in SmartRF Studio SWRC176. The DEVIATN register setting has no effect when using OOK.

5.12.1 Sync Word Qualifier

If sync word detection is enabled in the MDMCFG2 register, the CC113L will not start filling the RX FIFO and perform the packet filtering described in Section 5.10.2 before a valid sync word has been detected. The sync word qualifier mode is set by MDMCFG2.SYNC_MODE and is summarized in Table 5-8. Carrier sense described in Section 5.12.3.

5.12.2 RSSI

The RSSI value is an estimate of the signal power level in the chosen channel. This value is based on the current gain setting in the RX chain and the measured signal level in the channel.

In RX mode, the RSSI value can be read continuously from the RSSI status register until the demodulator detects a sync word (when sync word detection is enabled). At that point the RSSI readout value is frozen until the next time the chip enters the RX state.

The RSSI value is given in dBm with a ½-dB resolution. The RSSI update rate, f_RSSI, depends on the receiver filter bandwidth (BW_channel is defined in Section 5.8) and AGCCTRL0.FILTER_LENGTH.

Equation 6.

If PKTLEN.APPEND_STATUS is enabled, the last RSSI value of the packet is automatically added to the first byte appended after the payload.

The RSSI value read from the RSSI status register is a 2s complement number. The following procedure can be used to convert the RSSI reading to an absolute power level (RSSI_dBm).

1. Read the RSSI status register
2. Convert the reading from a hexadecimal number to a decimal number (RSSI_dec)
3. If RSSI_dec ≥ 128 then RSSI_dBm = (RSSI_dec - 256)/2 – RSSI_offset
4. Else if RSSI_dec < 128 then RSSI_dBm = (RSSI_dec)/2 – RSSI_offset

Table 5-9 gives typical values for the RSSI_offset. Figure 5-9 and Figure 5-10 show typical plots of RSSI readings as a function of input power level for different data rates.

Figure 5-9 Typical RSSI Value Versus Input Power Level for Different Data Rates at 433 MHz

Figure 5-10 Typical RSSI Value Versus Input Power Level for Different Data Rates at 868 MHz

5.12.3 Carrier Sense (CS)

Carrier sense (CS) is used as a sync word qualifier and can be asserted based on two conditions which can be individually adjusted:

• CS is asserted when the RSSI is above a programmable absolute threshold, and deasserted when RSSI is below the same threshold (with hysteresis). See more in Section 5.12.3.1.
• CS is asserted when the RSSI has increased with a programmable number of dB from one RSSI sample to the next, and de-asserted when RSSI has decreased with the same number of dB. This setting is not dependent on the absolute signal level and is thus useful to detect signals in environments with time varying noise floor. See more in Section 5.12.3.2.

Carrier sense can be used as a sync word qualifier that requires the signal level to be higher than the threshold for a sync word search to be performed and is set by setting MDMCFG2. The carrier sense signal can be observed on one of the GDO pins by setting IOCFGx.GDOx_CFG=14 and in the status register bit PKTSTATUS.CS.

5.13.1 Power-On Start-Up Sequence

When the power supply is turned on, the system must be reset. This is achieved by one of the two sequences described below, that is, automatic power-on reset (POR) or manual reset. After the automatic power-on reset or manual reset, it is also recommended to change the signal that is output on the GDO0 pin. The default setting is to output a clock signal with a frequency of CLK_XOSC/192. However, to optimize performance in RX, an alternative GDO setting from the settings found in Table 5-15 should be selected.

5.13.1.1 Automatic POR

A power-on reset circuit is included in the CC113L. The minimum requirements stated in Section 4.10 must be followed for the power-on reset to function properly. The internal power-up sequence is completed when CHIP_RDYn goes low. CHIP_RDYn is observed on the SO pin after CSn is pulled low. See Section 5.5.1 for more details on CHIP_RDYn.

When the CC113L reset is completed, the chip will be in the IDLE state and the crystal oscillator will be running. If the chip has had sufficient time for the crystal oscillator to stabilize after the power-on-reset, the SO pin will go low immediately after taking CSn low. If CSn is taken low before reset is completed, the SO pin will first go high, indicating that the crystal oscillator is not stabilized, before going low as shown in Figure 5-12.

Figure 5-12 Power-On Reset with SRES

5.13.1.2 Manual Reset

The other global reset possibility on CC113L uses the SRES command strobe. By issuing this strobe, all internal registers and states are set to the default, IDLE state. The manual power-up sequence is as follows (see Figure 5-13):

• Set SCLK = 1 and SI = 0.
• Strobe CSn low / high.
• Hold CSn low and then high for at least 40 µs relative to pulling CSn low
• Pull CSn low and wait for SO to go low (CHIP_RDYn).
• Issue the SRES strobe on the SI line.
• When SO goes low again, reset is complete and the chip is in the IDLE state.

XOSC and voltage regulator switched on

Figure 5-13 Power-On Reset with SRES

NOTE

The above reset procedure is only required just after the power supply is first turned on. If the user wants to reset the CC113L after this, it is only necessary to issue an SRES command strobe.

5.13.2 Crystal Control

The crystal oscillator (XOSC) is either automatically controlled or always on, if MCSM0.XOSC_FORCE_ON is set.

In the automatic mode, the XOSC will be turned off if the SXOFF or SPWD command strobes are issued; the state machine then goes to XOFF or SLEEP respectively. This can only be done from the IDLE state. The XOSC will be turned off when CSn is released (goes high). The XOSC will be automatically turned on again when CSn goes low. The state machine will then go to the IDLE state. The SO pin on the SPI interface must be pulled low before the SPI interface is ready to be used as described in Section 5.5.1.

If the XOSC is forced on, the crystal will always stay on even in the SLEEP state.

Crystal oscillator start-up time depends on crystal ESR and load capacitances. The electrical specification for the crystal oscillator can be found in Section 4.7.

5.13.3 Voltage Regulator Control

The voltage regulator to the digital core is controlled by the radio controller. When the chip enters the SLEEP state which is the state with the lowest current consumption, the voltage regulator is disabled. This occurs after CSn is released when a SPWD command strobe has been sent on the SPI interface. The chip is then in the SLEEP state. Setting CSn low again will turn on the regulator and crystal oscillator and make the chip enter the IDLE state.

5.13.4 Receive Mode (RX)

Receive mode is activated directly by the MCU by using the SRX command strobe.

The frequency synthesizer must be calibrated regularly. CC113L has one manual calibration option (using the SCAL strobe), and three automatic calibration options that are controlled by the MCSM0.FS_AUTOCAL setting:

• Calibrate when going from IDLE to RX
• Calibrate when going from RX to IDLE automatically (not forced in IDLE by issuing an SIDLE strobe)
• Calibrate every fourth time when going from RX to IDLE automatically (not forced in IDLE by issuing an SIDLE strobe)

If the radio goes from RX to IDLE by issuing an SIDLE strobe, calibration will not be performed. The calibration takes a constant number of XOSC cycles; see Table 5-12 for timing details regarding calibration.

When RX is activated, the chip will remain in receive mode until a packet is successfully received or until RX mode terminated due to lack of carrier sense (see Section 18.5). The probability that a false sync word is detected can be reduced by using CS together with maximum sync word length as described in Section 17. After a packet is successfully received, the radio controller goes to the state indicated by the MCSM1.RXOFF_MODE setting. The possible destinations are:

• IDLE
• RX: Start search for a new packet

The SIDLE command strobe can always be used to force the radio controller to go to the IDLE state.

5.13.5 RX Termination

If the system expects the transmission to have started when entering RX mode, the MCSM2.RX_TIME_RSSI function can be used. The radio controller will then terminate RX if the first valid carrier sense sample indicates no carrier (RSSI below threshold). See Section 5.12.3 for details on Carrier Sense.

For OOK modulation, lack of carrier sense is only considered valid after eight symbol periods. Thus, the MCSM2.RX_TIME_RSSI function can be used in OOK mode when the distance between two “1” symbols is eight or less.

If RX terminates due to no carrier sense when the MCSM2.RX_TIME_RSSI function is used, the radio will always go back to IDLE, regardless of the MCSM1.RXOFF_MODE setting.

5.13.6 Timing

Table 5-14 FIFO_THR Settings and the Corresponding FIFO Thresholds

5.16.1 VCO and PLL Self-Calibration

The VCO characteristics vary with temperature and supply voltage changes as well as the desired operating frequency. In order to ensure reliable operation, CC113L includes frequency synthesizer self-calibration circuitry. This calibration should be done regularly, and must be performed after turning on power and before using a new frequency (or channel). The number of XOSC cycles for completing the PLL calibration is given in Table 5-12.

The calibration can be initiated automatically or manually. The synthesizer can be automatically calibrated each time the synthesizer is turned on, or each time the synthesizer is turned off automatically. This is configured with the MCSM0.FS_AUTOCAL register setting. In manual mode, the calibration is initiated when the SCAL command strobe is activated in the IDLE mode.

To check that the PLL is in lock, the user can program register IOCFGx.GDOx_CFG to 0x0A, and use the lock detector output available on the GDOx pin as an interrupt for the MCU (x = 0,1, or 2). A positive transition on the GDOx pin means that the PLL is in lock. As an alternative the user can read register FSCAL1. The PLL is in lock if the register content is different from 0x3F. Refer also to the CC113L Errata Notes SWRZ038.

For more robust operation, the source code could include a check so that the PLL is re-calibrated until PLL lock is achieved if the PLL does not lock the first time.

Table 5-15 GDOx Signal Selection (x = 0, 1, or 2)

5.19.1 Asynchronous Serial Operation

Asynchronous transfer is included in the CC113L for backward compatibility with systems that are already using the asynchronous data transfer.

When asynchronous transfer is enabled, all packet handling support is disabled and it is not possible to use Manchester encoding.

Asynchronous serial mode is enabled by setting PKTCTRL0.PKT_FORMAT to 3. Data output can be on GDO0, GDO1, or GDO2. This is set by the IOCFG0.GDO0_CFG, IOCFG1.GDO1_CFG and IOCFG2.GDO2_CFG fields.

In asynchronous serial mode no data decision is done on-chip and the raw data is put on the data output line. When using asynchronous serial mode make sure the interfacing MCU does proper oversampling and that it can handle the jitter on the data output line. The MCU should tolerate a jitter of ±1/8 of a bit period as the data stream is time-discrete using 8 samples per bit.

In asynchronous serial mode there will be glitches of 37 - 38.5 ns duration (1/XOSC) occurring infrequently and with random periods. A simple RC filter can be added to the data output line between CC113L and the MCU to get rid of the 37 - 38.5 ns glitches if considered a problem. The filter 3 dB cut-off frequency needs to be high enough so that the data is not filtered and at the same time low enough to remove the glitch. As an example, for 2.4 kBaud data rate a 1 kΩ resistor and 2.7 nF capacitor can be used. This gives a 3 dB cut-off frequency of 59 kHz.

5.19.2 Synchronous Serial Operation

Setting PKTCTRL0.PKT_FORMAT to 1 enables synchronous serial mode. When using this mode, sync detection should be disabled together with CRC calculation (MDMCFG2.SYNC_MODE=000 and PKTCTRL0.CRC_EN=0). Infinite packet length mode should be used (PKTCTRL0.LENGTH_CONFIG=10b).

In synchronous serial mode, data is transferred on a two-wire serial interface. The CC113L provides a clock that is used to sample data on the data output line. The data output pin can be any of the GDO pins. This is set by the IOCFG0.GDO0_CFG, IOCFG1.GDO1_CFG, and IOCFG2.GDO2_CFG fields. The RX latency is 9 bits.

The MCU must handle preamble and sync word detection in software, together with CRC calculation.

5.20.1 SRD Regulations

International regulations and national laws regulate the use of radio receivers and transmitters. Short Range Devices (SRDs) for license free operation below 1 GHz are usually operated in the 315 MHz, 433 MHz, 868 MHz or 915 MHz frequency bands. The CC113L is specifically designed for such use with its 300 - 348 MHz, 387 - 464 MHz, and 779 - 928 MHz operating ranges. The most important regulations when using the CC113L in the 315 MHz, 433 MHz, 868 MHz, or 915 MHz frequency bands are EN 300 220 V2.3.1 (Europe) and FCC CFR47 part 15 (USA).

For compliance with modulation bandwidth requirements under EN 300 220 V2.3.1 in the 863 to 870 MHz frequency range it is recommended to use a 26 MHz crystal for frequencies below 869 MHz and a 27 MHz crystal for frequencies above 869 MHz.

Please note that compliance with regulations is dependent on the complete system performance. It is the customer’s responsibility to ensure that the system complies with regulations.

5.20.2 Calibration in Multi-Channel Systems

CC113L is highly suited for multi-channel systems due to its agile frequency synthesizer and effective communication interface.

Charge pump current, VCO current, and VCO capacitance array calibration data is required for each frequency when implementing a multi-channel system. There are 3 ways of obtaining the calibration data from the chip:

1. Calibration for every frequency change. The PLL calibration time is 712/724 μs (26 MHz crystal and TEST0 = 0x09/0B, see Table 5-13). The blanking interval between each frequency is then 787/799 μs.
2. Perform all necessary calibration at startup and store the resulting FSCAL3, FSCAL2, and FSCAL1 register values in MCU memory. The VCO capacitance calibration FSCAL1 register value must be found for each RF frequency to be used. The VCO current calibration value and the charge pump current calibration value available in FSCAL2 and FSCAL3 respectively are not dependent on the RF frequency, so the same value can therefore be used for all RF frequencies for these two registers. Between each frequency change, the calibration process can then be replaced by writing the FSCAL3, FSCAL2 and FSCAL1 register values that corresponds to the next RF frequency. The PLL turn on time is approximately 75 μs (Table 5-12). The blanking interval between each frequency hop is then approximately 75 μs.
3. Run calibration on a single frequency at startup. Next write 0 to FSCAL3[5:4] to disable the charge pump calibration. After writing to FSCAL3[5:4], strobe SRX with MCSM0.FS_AUTOCAL=1 for each new frequency. That is, VCO current and VCO capacitance calibration is done, but not charge pump current calibration. When charge pump current calibration is disabled the calibration time is reduced from 712/724 μs to 145/157 μs (26 MHz crystal and TEST0 = 0x09/0B, see Table 5-13). The blanking interval between each frequency hop is then 220/232 μs.

There is a trade-off between blanking time and memory space needed for storing calibration data in non-volatile memory. Solution 2) above gives the shortest blanking interval, but requires more memory space to store calibration values. This solution also requires that the supply voltage and temperature do not vary much in order to have a robust solution. Solution 3) gives 567 μs smaller blanking interval than solution 1).

The recommended settings for TEST0.VCO_SEL_CAL_EN change with frequency. This means that one should always use SmartRF Studio [4] to get the correct settings for a specific frequency before doing a calibration, regardless of which calibration method is being used.

Table 5-16 Command Strobes

Table 5-17 Configuration Registers Overview

Table 5-18 Status Registers Overview

Table 5-19 SPI Address Space

5.21.1 Configuration Register Details - Registers with preserved values in SLEEP state

Table 5-31 0x0B: FSCTRL1 - Frequency Synthesizer Control

Bit	Field Name	Reset	R/W	Description
7:6			R0	Not used
5		0	R/W	Use setting from SmartRF Studio
4:0	FREQ_IF[4:0]	15 (01111)	R/W	The desired IF frequency to employ in RX. Subtracted from FS base frequency in RX and controls the digital complex mixer in the demodulator. The default value gives an IF frequency of 381kHz, assuming a 26.0 MHz crystal.

Table 5-33 0x0D: FREQ2 - Frequency Control Word, High Byte

Bit	Field Name	Reset	R/W	Description
7:6	FREQ[23:22]	0 (00)	R	FREQ[23:22] is always 0 (the FREQ2 register is less than 36 with 26 - 27 MHz crystal)
5:0	FREQ[21:16]	30 (011110)	R/W	FREQ[23:0] is the base frequency for the frequency synthesizer in increments of fXOSC/216.

Table 5-36 0x10: MDMCFG4 - Modem Configuration

Bit	Field Name	Reset	R/W	Description
7:6	CHANBW_E[1:0]	2 (10)	R/W
5:4	CHANBW_M[1:0]	0 (00)	R/W	Sets the decimation ratio for the delta-sigma ADC input stream and thus the channel bandwidth. The default values give 203 kHz channel filter bandwidth, assuming a 26.0 MHz crystal.
3:0	DRATE_E[3:0]	12 (1100)	R/W	The exponent of the user specified symbol rate

Table 5-37 0x11: MDMCFG3 - Modem Configuration

Bit	Field Name	Reset	R/W	Description
7:0	DRATE_M[7:0]	34 (0x22)	R/W	The mantissa of the user specified symbol rate. The symbol rate is configured using an unsigned, floating-point number with 9-bit mantissa and 4-bit exponent. The 9th bit is a hidden ‘1’. The resulting data rate is: The default values give a data rate of 115.051 kBaud (closest setting to 115.2 kBaud), assuming a 26.0 MHz crystal.

Table 5-40 0x14: MDMCFG0 - Modem Configuration

Bit	Field Name	Reset	R/W	Description
7:0	CHANSPC_M[7:0]	248 (0xF8)	R/W	8-bit mantissa of channel spacing. The channel spacing is multiplied by the channel number CHAN and added to the base frequency. It is unsigned and has the format: The default values give 199.951 kHz channel spacing (the closest setting to 200 kHz), assuming 26.0 MHz crystal frequency.

5.21.2 Configuration Register Details - Registers that Loose Programming in SLEEP State

5.21.3 Status Register Details