JAJSHI1B February   2019  – May 2021 CC3135

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 機能ブロック図
  5. 5 Revision History
  6. 6 Device Comparison
    1. 6.1 Related Products
  7. 7 Terminal Configuration and Functions
    1. 7.1 Pin Diagram
    2. 7.2 Pin Attributes
    3. 7.3 Signal Descriptions
      1.      12
    4. 7.4 Connections for Unused Pins
  8. 8 Specifications
    1. 8.1  Absolute Maximum Ratings
    2. 8.2  ESD Ratings
    3. 8.3  Power-On Hours (POH)
    4. 8.4  Recommended Operating Conditions
    5. 8.5  Current Consumption Summary: 2.4 GHz RF Band
    6. 8.6  Current Consumption Summary: 5 GHz RF Band
    7. 8.7  TX Power Control for 2.4 GHz Band
    8. 8.8  TX Power Control for 5 GHz
    9. 8.9  Brownout and Blackout Conditions
      1.      24
    10. 8.10 Electrical Characteristics for DIO Pins
      1.      26
      2.      27
    11. 8.11 Electrical Characteristics for Pin Internal Pullup and Pulldown
    12. 8.12 WLAN Receiver Characteristics
      1.      30
      2.      31
    13. 8.13 WLAN Transmitter Characteristics
      1.      33
      2.      34
    14. 8.14 WLAN Transmitter Out-of-Band Emissions
      1.      36
      2.      37
    15. 8.15 BLE/2.4 GHz Radio Coexistence and WLAN Coexistence Requirements
    16. 8.16 Thermal Resistance Characteristics for RGK Package
    17. 8.17 Timing and Switching Characteristics
      1. 8.17.1 Power Supply Sequencing
      2. 8.17.2 Device Reset
      3. 8.17.3 Reset Timing
        1. 8.17.3.1 nRESET (32-kHz Crystal)
        2.       45
        3. 8.17.3.2 nRESET (External 32-kHz Crystal)
          1.        47
      4. 8.17.4 Wakeup From HIBERNATE Mode
        1.       49
      5. 8.17.5 Clock Specifications
        1. 8.17.5.1 Slow Clock Using Internal Oscillator
          1.        52
        2. 8.17.5.2 Slow Clock Using an External Clock
          1.        54
        3. 8.17.5.3 Fast Clock (Fref) Using an External Crystal
          1.        56
        4. 8.17.5.4 Fast Clock (Fref) Using an External Oscillator
          1.        58
      6. 8.17.6 Interfaces
        1. 8.17.6.1 Host SPI Interface Timing
          1.        61
        2. 8.17.6.2 Flash SPI Interface Timing
          1.        63
        3. 8.17.6.3 DIO Interface Timing
          1. 8.17.6.3.1 DIO Output Transition Time Parameters (Vsupply = 3.3 V)
            1.         66
          2. 8.17.6.3.2 DIO Input Transition Time Parameters
            1.         68
    18. 8.18 External Interfaces
      1. 8.18.1 SPI Flash Interface
      2. 8.18.2 SPI Host Interface
      3. 8.18.3 Host UART Interface
        1. 8.18.3.1 5-Wire UART Topology
        2. 8.18.3.2 4-Wire UART Topology
        3. 8.18.3.3 3-Wire UART Topology
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Device Features
      1. 9.2.1 WLAN
      2. 9.2.2 Network Stack
      3. 9.2.3 Security
      4. 9.2.4 Host Interface and Driver
      5. 9.2.5 System
    3. 9.3 FIPS 140-2 Level 1 Certification
    4. 9.4 Power-Management Subsystem
      1. 9.4.1 VBAT Wide-Voltage Connection
    5. 9.5 Low-Power Operating Modes
      1. 9.5.1 Low-Power Deep Sleep
      2. 9.5.2 Hibernate
      3. 9.5.3 Shutdown
    6. 9.6 Memory
      1. 9.6.1 External Memory Requirements
    7. 9.7 Restoring Factory Default Configuration
    8. 9.8 Hostless Mode
  10. 10Applications, Implementation, and Layout
    1. 10.1 Application Information
      1. 10.1.1 BLE/2.4 GHz Radio Coexistence
      2. 10.1.2 Antenna Selection
      3. 10.1.3 Typical Application
    2. 10.2 PCB Layout Guidelines
      1. 10.2.1 General PCB Guidelines
      2. 10.2.2 Power Layout and Routing
        1. 10.2.2.1 Design Considerations
      3. 10.2.3 Clock Interface Guidelines
      4. 10.2.4 Digital Input and Output Guidelines
      5. 10.2.5 RF Interface Guidelines
  11. 11Device and Documentation Support
    1. 11.1  Third-Party Products Disclaimer
    2. 11.2  Tools and Software
    3. 11.3  Firmware Updates
    4. 11.4  Device Nomenclature
    5. 11.5  Documentation Support
    6. 11.6  サポート・リソース
    7. 11.7  Trademarks
    8. 11.8  Electrostatic Discharge Caution
    9. 11.9  Export Control Notice
    10. 11.10 Glossary
  12. 12Mechanical, Packaging, and Orderable Information
    1. 12.1 Packaging Information
    2. 12.2 Package Option Addendum
      1. 12.2.1 Packaging Information
      2. 12.2.2 Tape and Reel Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

Table 7-2 Signal Descriptions
FUNCTION SIGNAL NAME PIN
NO.		 PIN
TYPE		 SIGNAL DIRECTION DESCRIPTION
Antenna selection DIO10 1 I/O O Antenna selection control
DIO12 3 I/O O
DIO13 4 I/O O
DIO23 16 I/O O
DIO24 17 I/O O
DIO28 18(1) I/O O
DIO29 20 I/O O
DIO25 21 O O
DIO31 45(1) I/O O
DIO32 52(1) I/O O
DIO30 53(1) I/O O
DIO3 58 I/O O
DIO4 59 I/O O
DIO5 60 I/O O
DIO8 63 I/O O
DIO9 64 I/O O
BLE/2.4 GHz Radio coexistence DIO10 1 I/O I/O Coexistence inputs and outputs
DIO12 3 I/O I/O
DIO13 4 I/O I/O
DIO23 16 I/O I/O
DIO24 17 I/O I/O
DIO28 18(1) I/O I/O
DIO29 20 I/O I/O
DIO25 21 O O
DIO31 45(1) I/O I/O
DIO32 52(1) I/O I/O
DIO30 53(1) I/O I/O
DIO3 58 I/O I/O
DIO4 59 I/O I/O
DIO5 60 I/O I/O
DIO8 63 I/O I/O
DIO9 64 I/O I/O
Clock WLAN_XTAL_N 22 — — 40-MHz crystal; pull down if external TCXO is used
WLAN_XTAL_P 23 — — 40-MHz crystal or TCXO clock input
RTC_XTAL_P 51 — — Connect 32.768-kHz crystal or force external CMOS level clock
RTC_XTAL_N 52 — — Connect 32.768-kHz crystal or connect 100-kΩ resistor to supply voltage
Hostless Mode DIO10 1 I/O I/O Hostless mode inputs and outputs
DIO12 3 I/O I/O
DIO13 4 I/O I/O
DIO23 16 I/O I/O
DIO24 17 I/O I/O
DIO28 18(1) I/O I/O
DIO29 20 I/O I/O
DIO25 21 O O
DIO31 45(1) I/O I/O
DIO32 52(1) I/O I/O
DIO30 53(1) I/O I/O
DIO3 58 I/O I/O
DIO4 59 I/O I/O
DIO5 60 I/O I/O
DIO8 63 I/O I/O
DIO9 64 I/O I/O
Power VDD_DIG1 9 — — Internal digital core voltage
VIN_IO1 10 — — Device supply voltage (VBAT)
VDD_PLL 24 — — Internal analog voltage
LDO_IN2 25 — — Internal analog RF supply from analog DC/DC output
VDD_PA_IN 33 — — Internal PA supply voltage from PA DC/DC output
LDO_IN1 36 — — Internal analog RF supply from analog DC/DC output
VIN_DCDC_ANA 37 — — Analog DC/DC input (connected to device input supply [VBAT])
DCDC_ANA_SW 38 — — Internal analog DC/DC switching node
VIN_DCDC_PA 39 — — PA DC/DC input (connected to device input supply [VBAT])
DCDC_PA_SW_P 40 — — Internal PA DC/DC switching node
DCDC_PA_SW_N 41 — — Internal PA DC/DC switching node
DCDC_PA_OUT 42 — — Internal PA buck converter output
DCDC_DIG_SW 43 — — Internal digital DC/DC switching node
VIN_DCDC_DIG 44 — — Digital DC/DC input (connected to device input supply [VBAT])
DCDC_ANA2_SW_P 45 — — Analog to DC/DC converter +ve switching node
DCDC_ANA2_SW_N 46 — — Internal analog to DC/DC converter –ve switching node
VDD_ANA2 47 — — Internal analog to DC/DC output
VDD_ANA1 48 — — Internal analog supply fed by ANA2 DC/DC output
VDD_RAM 49 — — Internal SRAM LDO output
VIN_IO2 54 — — Device supply voltage (VBAT)
VDD_DIG2 56 — — Internal digital core voltage
HOST SPI HOST_SPI_CLK 5 I/O I Host SPI clock input
HOST_SPI_MOSI 6 I/O I Data from Host
HOST_SPI_MISO 8 I/O O Data to Host
HOST_SPI_nCS 7 I/O I Device select (active low)
FLASH SPI FLASH_SPI_CLK 11 O O Clock to SPI serial flash (fixed default)
FLASH_SPI_DOUT 12 O O Data to SPI serial flash (fixed default)
FLASH_SPI_DIN 13 I I Data from SPI serial flash (fixed default)
FLASH_SPI_CS 14 O O Device select to SPI serial flash (fixed default)
UART UART1_nRTS 50 I/O O UART1 request-to-send (active low)
UART1_TX 55 I/O I UART TX data
UART1_RX 57 I/O O UART RX data
UART1_nCTS 61 I/O I UART1 clear-to-send (active low)
Sense-On-Power SOP2 21(2) O I Sense-on-power 2
SOP1 34 I I Configuration sense-on-power 1
SOP0 35 I I Configuration sense-on-power 0
Reset nRESET 32 I I Global master device reset (active low)
nHIB nHIB 2 I I Hibernate signal input to the NWP subsystem (active low)
RF A_RX 27 I I WLAN analog A-band receive
A_TX 28 O O WLAN analog A-band transmit
RF_BG 31 I/O I/O WLAN analog RF 802.11 b/g bands
Test Port TEST_58 58 O O Test Signal
TEST_59 59 I I Test Signal
TEST_60 60 O O Test Signal
TEST_62 62 O O Test Signal
(1) LPDS retention unavailable.
(2) This pin has dual functions: as a SOP[2] (device operation mode), and as an external TCXO enable. As a TXCO enable, the pin is an output on power up and driven logic high. During hibernate low-power mode, the pin is in a Hi-Z state but is pulled down for SOP mode to disable TCXO. Because of the SOP functionality, the pin must be used as an output only.