JAJSHI1B
February 2019 – May 2021
CC3135
PRODUCTION DATA
1
特長
2
アプリケーション
3
概要
4
機能ブロック図
5
Revision History
6
Device Comparison
6.1
Related Products
7
Terminal Configuration and Functions
7.1
Pin Diagram
7.2
Pin Attributes
7.3
Signal Descriptions
12
7.4
Connections for Unused Pins
8
Specifications
8.1
Absolute Maximum Ratings
8.2
ESD Ratings
8.3
Power-On Hours (POH)
8.4
Recommended Operating Conditions
8.5
Current Consumption Summary: 2.4 GHz RF Band
8.6
Current Consumption Summary: 5 GHz RF Band
8.7
TX Power Control for 2.4 GHz Band
8.8
TX Power Control for 5 GHz
8.9
Brownout and Blackout Conditions
24
8.10
Electrical Characteristics for DIO Pins
26
27
8.11
Electrical Characteristics for Pin Internal Pullup and Pulldown
8.12
WLAN Receiver Characteristics
30
31
8.13
WLAN Transmitter Characteristics
33
34
8.14
WLAN Transmitter Out-of-Band Emissions
36
37
8.15
BLE/2.4 GHz Radio Coexistence and WLAN Coexistence Requirements
8.16
Thermal Resistance Characteristics for RGK Package
8.17
Timing and Switching Characteristics
8.17.1
Power Supply Sequencing
8.17.2
Device Reset
8.17.3
Reset Timing
8.17.3.1
nRESET (32-kHz Crystal)
45
8.17.3.2
nRESET (External 32-kHz Crystal)
47
8.17.4
Wakeup From HIBERNATE Mode
49
8.17.5
Clock Specifications
8.17.5.1
Slow Clock Using Internal Oscillator
52
8.17.5.2
Slow Clock Using an External Clock
54
8.17.5.3
Fast Clock (Fref) Using an External Crystal
56
8.17.5.4
Fast Clock (Fref) Using an External Oscillator
58
8.17.6
Interfaces
8.17.6.1
Host SPI Interface Timing
61
8.17.6.2
Flash SPI Interface Timing
63
8.17.6.3
DIO Interface Timing
8.17.6.3.1
DIO Output Transition Time Parameters (Vsupply = 3.3 V)
66
8.17.6.3.2
DIO Input Transition Time Parameters
68
8.18
External Interfaces
8.18.1
SPI Flash Interface
8.18.2
SPI Host Interface
8.18.3
Host UART Interface
8.18.3.1
5-Wire UART Topology
8.18.3.2
4-Wire UART Topology
8.18.3.3
3-Wire UART Topology
9
Detailed Description
9.1
Overview
9.2
Device Features
9.2.1
WLAN
9.2.2
Network Stack
9.2.3
Security
9.2.4
Host Interface and Driver
9.2.5
System
9.3
FIPS 140-2 Level 1 Certification
9.4
Power-Management Subsystem
9.4.1
VBAT Wide-Voltage Connection
9.5
Low-Power Operating Modes
9.5.1
Low-Power Deep Sleep
9.5.2
Hibernate
9.5.3
Shutdown
9.6
Memory
9.6.1
External Memory Requirements
9.7
Restoring Factory Default Configuration
9.8
Hostless Mode
10
Applications, Implementation, and Layout
10.1
Application Information
10.1.1
BLE/2.4 GHz Radio Coexistence
10.1.2
Antenna Selection
10.1.3
Typical Application
10.2
PCB Layout Guidelines
10.2.1
General PCB Guidelines
10.2.2
Power Layout and Routing
10.2.2.1
Design Considerations
10.2.3
Clock Interface Guidelines
10.2.4
Digital Input and Output Guidelines
10.2.5
RF Interface Guidelines
11
Device and Documentation Support
11.1
Third-Party Products Disclaimer
11.2
Tools and Software
11.3
Firmware Updates
11.4
Device Nomenclature
11.5
Documentation Support
11.6
サポート・リソース
11.7
Trademarks
11.8
Electrostatic Discharge Caution
11.9
Export Control Notice
11.10
Glossary
12
Mechanical, Packaging, and Orderable Information
12.1
Packaging Information
12.2
Package Option Addendum
12.2.1
Packaging Information
12.2.2
Tape and Reel Information
パッケージ・オプション
メカニカル・データ(パッケージ|ピン)
RGK|64
MPQF273C
サーマルパッド・メカニカル・データ
RGK|64
QFND565B
発注情報
jajshi1b_oa
8.2
ESD Ratings
VALUE
UNIT
V
ESD
Electrostatic discharge
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001
(1)
±2000
V
Charged device model (CDM), per ANSI/ESDA/JEDEC JS-002
(2)
±500
(1)
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2)
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.