JAJSHI1B February   2019  – May 2021 CC3135

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 機能ブロック図
  5. 5 Revision History
  6. 6 Device Comparison
    1. 6.1 Related Products
  7. 7 Terminal Configuration and Functions
    1. 7.1 Pin Diagram
    2. 7.2 Pin Attributes
    3. 7.3 Signal Descriptions
      1.      12
    4. 7.4 Connections for Unused Pins
  8. 8 Specifications
    1. 8.1  Absolute Maximum Ratings
    2. 8.2  ESD Ratings
    3. 8.3  Power-On Hours (POH)
    4. 8.4  Recommended Operating Conditions
    5. 8.5  Current Consumption Summary: 2.4 GHz RF Band
    6. 8.6  Current Consumption Summary: 5 GHz RF Band
    7. 8.7  TX Power Control for 2.4 GHz Band
    8. 8.8  TX Power Control for 5 GHz
    9. 8.9  Brownout and Blackout Conditions
      1.      24
    10. 8.10 Electrical Characteristics for DIO Pins
      1.      26
      2.      27
    11. 8.11 Electrical Characteristics for Pin Internal Pullup and Pulldown
    12. 8.12 WLAN Receiver Characteristics
      1.      30
      2.      31
    13. 8.13 WLAN Transmitter Characteristics
      1.      33
      2.      34
    14. 8.14 WLAN Transmitter Out-of-Band Emissions
      1.      36
      2.      37
    15. 8.15 BLE/2.4 GHz Radio Coexistence and WLAN Coexistence Requirements
    16. 8.16 Thermal Resistance Characteristics for RGK Package
    17. 8.17 Timing and Switching Characteristics
      1. 8.17.1 Power Supply Sequencing
      2. 8.17.2 Device Reset
      3. 8.17.3 Reset Timing
        1. 8.17.3.1 nRESET (32-kHz Crystal)
        2.       45
        3. 8.17.3.2 nRESET (External 32-kHz Crystal)
          1.        47
      4. 8.17.4 Wakeup From HIBERNATE Mode
        1.       49
      5. 8.17.5 Clock Specifications
        1. 8.17.5.1 Slow Clock Using Internal Oscillator
          1.        52
        2. 8.17.5.2 Slow Clock Using an External Clock
          1.        54
        3. 8.17.5.3 Fast Clock (Fref) Using an External Crystal
          1.        56
        4. 8.17.5.4 Fast Clock (Fref) Using an External Oscillator
          1.        58
      6. 8.17.6 Interfaces
        1. 8.17.6.1 Host SPI Interface Timing
          1.        61
        2. 8.17.6.2 Flash SPI Interface Timing
          1.        63
        3. 8.17.6.3 DIO Interface Timing
          1. 8.17.6.3.1 DIO Output Transition Time Parameters (Vsupply = 3.3 V)
            1.         66
          2. 8.17.6.3.2 DIO Input Transition Time Parameters
            1.         68
    18. 8.18 External Interfaces
      1. 8.18.1 SPI Flash Interface
      2. 8.18.2 SPI Host Interface
      3. 8.18.3 Host UART Interface
        1. 8.18.3.1 5-Wire UART Topology
        2. 8.18.3.2 4-Wire UART Topology
        3. 8.18.3.3 3-Wire UART Topology
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Device Features
      1. 9.2.1 WLAN
      2. 9.2.2 Network Stack
      3. 9.2.3 Security
      4. 9.2.4 Host Interface and Driver
      5. 9.2.5 System
    3. 9.3 FIPS 140-2 Level 1 Certification
    4. 9.4 Power-Management Subsystem
      1. 9.4.1 VBAT Wide-Voltage Connection
    5. 9.5 Low-Power Operating Modes
      1. 9.5.1 Low-Power Deep Sleep
      2. 9.5.2 Hibernate
      3. 9.5.3 Shutdown
    6. 9.6 Memory
      1. 9.6.1 External Memory Requirements
    7. 9.7 Restoring Factory Default Configuration
    8. 9.8 Hostless Mode
  10. 10Applications, Implementation, and Layout
    1. 10.1 Application Information
      1. 10.1.1 BLE/2.4 GHz Radio Coexistence
      2. 10.1.2 Antenna Selection
      3. 10.1.3 Typical Application
    2. 10.2 PCB Layout Guidelines
      1. 10.2.1 General PCB Guidelines
      2. 10.2.2 Power Layout and Routing
        1. 10.2.2.1 Design Considerations
      3. 10.2.3 Clock Interface Guidelines
      4. 10.2.4 Digital Input and Output Guidelines
      5. 10.2.5 RF Interface Guidelines
  11. 11Device and Documentation Support
    1. 11.1  Third-Party Products Disclaimer
    2. 11.2  Tools and Software
    3. 11.3  Firmware Updates
    4. 11.4  Device Nomenclature
    5. 11.5  Documentation Support
    6. 11.6  サポート・リソース
    7. 11.7  Trademarks
    8. 11.8  Electrostatic Discharge Caution
    9. 11.9  Export Control Notice
    10. 11.10 Glossary
  12. 12Mechanical, Packaging, and Orderable Information
    1. 12.1 Packaging Information
    2. 12.2 Package Option Addendum
      1. 12.2.1 Packaging Information
      2. 12.2.2 Tape and Reel Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

7.2 Pin Attributes

Table 7-1 describes the CC3135 pins.

Note:

Digital IOs on the CC3135 device refer to hostless mode, BLE/2.4 GHz coexistence, and antenna select IOs, not general-purpose IOs.

If an external device drives a positive voltage to signal pads when the CC3135 device is not powered, DC current is drawn from the other device. If the drive strength of the external device is adequate, an unintentional wakeup and boot of the CC3135 device can occur. To prevent current draw, TI recommends one of the following:

  • All devices interfaced to the CC3135 device must be powered from the same power rail as the CC3135 device.
  • Use level shifters between the CC3135 device and any external devices fed from other independent rails.
  • The nRESET pin of the CC3135 device must be held low until the VBAT supply to the device is driven and stable.
Table 7-1 Pin Description and Attributes
PIN DEFAULT FUNCTION DIGITAL I/O STATE AT RESET AND HIBERNATE I/O TYPE(1) DESCRIPTION
PAD_
CONFIG		 HOSTLESS MODE BLE COEX
CC_COEX_
OUT		 CC_COEX_
IN
1 DIO10 10 Y Y Y – I/O Digital input or output
2 nHIB 11 - - - Hi-Z I Hibernate signal input to the NWP subsystem (active low). This is connected to the MCU GPIO. If the GPIO from the MCU can float while the MCU enters low power, consider adding a pullup resistor on the board to avoid floating.
3 DIO12 12 Y Y Y – O Digital input or output
4 DIO13 13 Y Y Y – – Digital input or output
5 HOST_SPI_CLK 14 - - - Hi-Z I Host interface SPI clock
6 HOST_SPI_MOSI 15 - - - Hi-Z I Host interface SPI data input
7 HOST_SPI_MISO 16 - - - Hi-Z O Host interface SPI data output
8 HOST_SPI_nCS 17 - - - Hi-Z I Host interface SPI chip select (active low)
9 VDD_DIG1 - N/A N/A N/A Hi-Z Power Digital core supply (1.2 V)
10 VIN_IO1 - N/A N/A N/A Hi-Z Power I/O supply
11 FLASH_SPI_CLK - N/A N/A N/A Hi-Z O Serial Flash interface: SPI clock
12 FLASH_SPI_MOSI - N/A N/A N/A Hi-Z O Serial Flash interface: SPI data out
13 FLASH _SPI_MISO - N/A N/A N/A Hi-Z I Serial Flash interface: SPI data in (active high)
14 FLASH _SPI_CS - N/A N/A N/A Hi-Z O Serial Flash interface: SPI chip select (active low)
15 HOST_INTR 22 - - - Hi-Z O Interrupt output (active high)
16 DIO23 23 Y Y Y Hi-Z Digital input or output
17 DIO24 24 Y Y Y Hi-Z Digital input or output
18 DIO28 40 Y Y Y – – Digital input or output
19 Reserved 28 - - - Hi-Z – Connect a 100-kΩ pulldown resistor to ground.
20 DIO29 29 Y Y Y Hi-Z Digital input or output
21 SOP2/TCXO_EN(2) 25 Y(3) Y - Hi-Z O Controls restore to default mode. Enable signal for external TCXO. Add a 10-kΩ pulldown resistor to ground.
22 WLAN_XTAL_N - N/A N/A N/A Hi-Z Analog Connect the WLAN 40-MHz crystal here.
23 WLAN_XTAL_P - N/A N/A N/A Hi-Z Analog Connect the WLAN 40-MHz crystal here.
24 VDD_PLL - N/A N/A N/A Hi-Z Power Internal PLL power supply (1.4 V nominal)
25 LDO_IN2 - N/A N/A N/A Hi-Z Power Input to internal LDO
26 NC - N/A N/A N/A – – No Connect
27 A_RX - N/A N/A N/A – RF 5 GHz RF RX
28 A_TX - N/A N/A N/A – RF 5 GHz RF TX
29 GND - N/A N/A N/A – Power GND
30 GND - N/A N/A N/A – Power GND
31 RF_BG - N/A N/A N/A Hi-Z RF 2.4 GHz RF TX, RX
32 nRESET - N/A N/A N/A Hi-Z I RESET input for the device. Active low input. Use RC circuit (100 kΩ || 0.01 µF) for power on reset (POR).
33 VDD_PA_IN - N/A N/A N/A Hi-Z Power Power supply for the RF power amplifier (PA)
34 SOP1 - N/A N/A N/A Hi-Z – SOP[2:0] used for factory restore. Add 100-kΩ pulldown to ground. See Section 9.7. SOP1 used for 5 GHz switch control
35 SOP0 - N/A N/A N/A Hi-Z – SOP[2:0] used for factory restore. Add 100-kΩ pulldown to ground. See Section 9.7. SOP0 used for 5GHz switch control
36 LDO_IN1 - N/A N/A N/A Hi-Z Power Input to internal LDO
37 VIN_DCDC_ANA - N/A N/A N/A Hi-Z Power Power supply for the DC/DC converter for analog section
38 DCDC_ANA_SW - N/A N/A N/A Hi-Z Power Analog DC/DC converter switch output
39 VIN_DCDC_PA - N/A N/A N/A Hi-Z Power PA DC/DC converter input supply
40 DCDC_PA_SW_P - N/A N/A N/A Hi-Z Power PA DC/DC converter switch output +ve
41 DCDC_PA_SW_N - N/A N/A N/A Hi-Z Power PA DC/DC converter switch output –ve
42 DCDC_PA_OUT - N/A N/A N/A Hi-Z Power PA DC/DC converter output. Connect the output capacitor for DC/DC here.
43 DCDC_DIG_SW - N/A N/A N/A Hi-Z Power Digital DC/DC converter switch output
44 VIN_DCDC_DIG - N/A N/A N/A Hi-Z Power Power supply input for the digital DC/DC converter
45 DIO31 31 Y Y Y Hi-Z – Network Scripter I/O
46 DCDC_ANA2_SW_N - N/A N/A N/A Hi-Z Power Analog2 DC/DC converter switch output –ve
47 VDD_ANA2 - N/A N/A N/A Hi-Z Power Analog2 power supply input
48 VDD_ANA1 - N/A N/A N/A Hi-Z Power Analog1 power supply input
49 VDD_RAM - N/A N/A N/A Hi-Z Power Power supply for the internal RAM
50 UART1_nRTS 0 - - - Hi-Z O UART host interface (active low)
51 RTC_XTAL_P - N/A N/A N/A Hi-Z Analog 32.768-kHz XTAL_P or external CMOS level clock input
52 RTC_XTAL_N 32 Y Y Y Hi-Z Analog 32.768-kHz XTAL_N or 100-kΩ external pullup for external clock
53 DIO30 30 Y Y Y Hi-Z – Network Scripter I/O
54 VIN_IO2 N/A N/A N/A Hi-Z Power I/O power supply. Same as battery voltage.
55 UART1_TX 1 - - - Hi-Z O UART host interface. Connect to test point on prototype for Flash programming.
56 VDD_DIG2 - N/A Hi-Z Power Digital power supply (1.2 V)
57 UART1_RX 2 - - - Hi-Z I UART host interface; connect to test point on prototype for Flash programming.
58 TEST_58 3 Y Y Y Hi-Z O Test signal; connect to an external test point.
59 TEST_60 4 Y Y Y Hi-Z O Test signal; connect to an external test point.
60 TEST_60 5 Y Y Y Hi-Z O Test signal; connect to an external test point.
61 UART1_nCTS 6 - - - Hi-Z I UART host interface (active low)
62 TEST_62 7 - - - Hi-Z O Test signal; connect to an external test point.
63 DIO8 8 Y Y Y Hi-Z Digital input or output
64 DIO9 9 Y Y Y Hi-Z – Digital input or output
65 GND - N/A N/A N/A – Power Ground tab used as thermal and electrical ground
(1) I = input
O = output
RF = radio frequency
I/O = bidirectional
(2) This pin has dual functions: as a SOP[2] (device operation mode), and as an external TCXO enable. As a TXCO enable, the pin is an output on power up and driven logic high. During hibernate low-power mode, the pin is in a Hi-Z state but is pulled down for SOP mode to disable TCXO. Because of the SOP functionality, the pin must be used as an output only.
(3) Output Only