JAJSGL1C September   2016  – May 2021 CC3220R , CC3220S , CC3220SF

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 機能ブロック図
  5. 5 Revision History
  6. 6 Device Comparison
    1. 6.1 Related Products
  7. 7 Terminal Configuration and Functions
    1. 7.1 Pin Diagram
    2. 7.2 Pin Attributes and Pin Multiplexing
      1. 7.2.1 Pin Descriptions
    3. 7.3 Signal Descriptions
      1. 7.3.1 Signal Descriptions
    4. 7.4 Pin Multiplexing
    5. 7.5 Drive Strength and Reset States for Analog and Digital Multiplexed Pins
    6. 7.6 Pad State After Application of Power to Chip But Before Reset Release
    7. 7.7 Connections for Unused Pins
  8. 8 Specifications
    1. 8.1  Absolute Maximum Ratings
    2. 8.2  ESD Ratings
    3. 8.3  Power-On Hours (POH)
    4. 8.4  Recommended Operating Conditions
    5. 8.5  Current Consumption Summary (CC3220R, CC3220S)
    6. 8.6  Current Consumption Summary (CC3220SF)
    7. 8.7  TX Power and IBAT versus TX Power Level Settings
    8. 8.8  Brownout and Blackout Conditions
    9. 8.9  Electrical Characteristics (3.3 V, 25°C)
    10. 8.10 WLAN Receiver Characteristics
    11. 8.11 WLAN Transmitter Characteristics
    12. 8.12 WLAN Filter Requirements
      1. 8.12.1 WLAN Filter Requirements
    13. 8.13 Thermal Resistance Characteristics
      1. 8.13.1 Thermal Resistance Characteristics for RGK Package
    14. 8.14 Timing and Switching Characteristics
      1. 8.14.1 Power Supply Sequencing
      2. 8.14.2 Device Reset
      3. 8.14.3 Reset Timing
        1. 8.14.3.1 nRESET (32-kHz Crystal)
        2. 8.14.3.2 First-Time Power-Up and Reset Removal Timing Requirements (32-kHz Crystal)
        3. 8.14.3.3 nRESET (External 32-kHz)
          1. 8.14.3.3.1 First-Time Power-Up and Reset Removal Timing Requirements (External 32-kHz)
      4. 8.14.4 Wakeup From HIBERNATE Mode
      5. 8.14.5 Clock Specifications
        1. 8.14.5.1 Slow Clock Using Internal Oscillator
          1. 8.14.5.1.1 RTC Crystal Requirements
        2. 8.14.5.2 Slow Clock Using an External Clock
          1. 8.14.5.2.1 External RTC Digital Clock Requirements
        3. 8.14.5.3 Fast Clock (Fref) Using an External Crystal
          1. 8.14.5.3.1 WLAN Fast-Clock Crystal Requirements
        4. 8.14.5.4 Fast Clock (Fref) Using an External Oscillator
          1. 8.14.5.4.1 External Fref Clock Requirements (–40°C to +85°C)
      6. 8.14.6 Peripherals Timing
        1. 8.14.6.1  SPI
          1. 8.14.6.1.1 SPI Master
            1. 8.14.6.1.1.1 SPI Master Timing Parameters
          2. 8.14.6.1.2 SPI Slave
            1. 8.14.6.1.2.1 SPI Slave Timing Parameters
        2. 8.14.6.2  I2S
          1. 8.14.6.2.1 I2S Transmit Mode
            1. 8.14.6.2.1.1 I2S Transmit Mode Timing Parameters
          2. 8.14.6.2.2 I2S Receive Mode
            1. 8.14.6.2.2.1 I2S Receive Mode Timing Parameters
        3. 8.14.6.3  GPIOs
          1. 8.14.6.3.1 GPIO Output Transition Time Parameters (Vsupply = 3.3 V)
            1. 8.14.6.3.1.1 GPIO Output Transition Times (Vsupply = 3.3 V) (1) (1)
          2. 8.14.6.3.2 GPIO Output Transition Time Parameters (Vsupply = 1.85 V)
            1. 8.14.6.3.2.1 GPIO Output Transition Times (Vsupply = 1.85 V) (1) (1)
          3. 8.14.6.3.3 GPIO Input Transition Time Parameters
            1. 8.14.6.3.3.1 GPIO Input Transition Time Parameters'
        4. 8.14.6.4  I2C
          1. 8.14.6.4.1 I2C Timing Parameters (1)
        5. 8.14.6.5  IEEE 1149.1 JTAG
          1. 8.14.6.5.1 JTAG Timing Parameters
        6. 8.14.6.6  ADC
          1. 8.14.6.6.1 ADC Electrical Specifications
        7. 8.14.6.7  Camera Parallel Port
          1. 8.14.6.7.1 Camera Parallel Port Timing Parameters
        8. 8.14.6.8  UART
        9. 8.14.6.9  SD Host
        10. 8.14.6.10 Timers
  9. 9 Detailed Description
    1. 9.1 Arm® Cortex®-M4 Processor Core Subsystem
    2. 9.2 Wi-Fi Network Processor Subsystem
      1. 9.2.1 WLAN
      2. 9.2.2 Network Stack
    3. 9.3 Security
    4. 9.4 Power-Management Subsystem
      1. 9.4.1 VBAT Wide-Voltage Connection
      2. 9.4.2 Preregulated 1.85-V Connection
    5. 9.5 Low-Power Operating Mode
    6. 9.6 Memory
      1. 9.6.1 External Memory Requirements
      2. 9.6.2 Internal Memory
        1. 9.6.2.1 SRAM
        2. 9.6.2.2 ROM
        3. 9.6.2.3 Flash Memory
        4. 9.6.2.4 Memory Map
    7. 9.7 Restoring Factory Default Configuration
    8. 9.8 Boot Modes
      1. 9.8.1 Boot Mode List
  10. 10Applications, Implementation, and Layout
    1. 10.1 Application Information
      1. 10.1.1 Typical Application —CC3220x Wide-Voltage Mode
      2. 10.1.2 Typical Application Schematic—CC3220x Preregulated, 1.85-V Mode
    2. 10.2 PCB Layout Guidelines
      1. 10.2.1 General PCB Guidelines
      2. 10.2.2 Power Layout and Routing
        1. 10.2.2.1 Design Considerations
      3. 10.2.3 Clock Interfaces
      4. 10.2.4 Digital Input and Output
      5. 10.2.5 RF Interface
  11. 11Device and Documentation Support
    1. 11.1 Development Tools and Software
    2. 11.2 Firmware Updates
    3. 11.3 Device Nomenclature
    4. 11.4 Documentation Support
    5. 11.5 サポート・リソース
    6. 11.6 Trademarks
    7. 11.7 Electrostatic Discharge Caution
    8. 11.8 Export Control Notice
    9. 11.9 Glossary
  12. 12Mechanical, Packaging, and Orderable Information
    1. 12.1 Packaging Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

7.2.1 Pin Descriptions

PINSTYPEDESCRIPTIONSELECT AS WAKEUP SOURCECONFIGURE ADDITIONAL ANALOG MUXMUXED WITH JTAG
NO.NAME
1GPIO10I/OGeneral-purpose input or outputNoNoNo
2GPIO11I/OGeneral-purpose input or outputYesNoNo
3GPIO12I/OGeneral-purpose input or outputNoNoNo
4GPIO13I/OGeneral-purpose input or outputYesNoNo
5GPIO14I/OGeneral-purpose input or outputNoNoNo
6GPIO15I/OGeneral-purpose input or outputNoNoNo
7GPIO16I/OGeneral-purpose input or outputNoNoNo
8GPIO17I/OGeneral-purpose input or outputYesNoNo
9VDD_DIG1PowerInternal digital core voltageN/AN/AN/A
10VIN_IO1PowerI/O power supply (same as battery voltage)N/AN/AN/A
11FLASH_SPI_CLKOSerial flash interface: SPI clockN/AN/AN/A
12FLASH_SPI_DOUTOSerial flash interface: SPI data outN/AN/AN/A
13FLASH_SPI_DINISerial flash interface: SPI data inN/AN/AN/A
14FLASH_SPI_CSOSerial flash interface: SPI chip selectN/AN/AN/A
15GPIO22I/OGeneral-purpose input or outputNoNoNo
16TDII/OJTAG interface: data inputNoNoMuxed with JTAG TDI
17TDOI/OJTAG interface: data outputYesNoMuxed with JTAG TDO
18GPIO28I/OGeneral-purpose input or outputNoNoNo
19TCKI/OJTAG/SWD interface: clockNoNoMuxed with JTAG/
SWD-TCK
20TMSI/OJTAG/SWD interface: mode select or SWDIONoNoMuxed with JTAG/
SWD-TMSC
21(2)SOP2IConfiguration sense-on-power 2NoNoNo
22WLAN_XTAL_NAnalog40-MHz crystal. Pulldown if external TCXO is used.N/AN/AN/A
23WLAN_XTAL_PAnalog40-MHz crystal or TCXO clock inputN/AN/AN/A
24VDD_PLLPowerInternal analog voltageN/AN/AN/A
25LDO_IN2PowerInternal analog RF supply from analog DC/DC outputN/AN/AN/A
26NC—No connectN/AN/AN/A
27NC—ReservedN/AN/AN/A
28NC—ReservedN/AN/AN/A
29(1)ANTSEL1OAntenna selection controlNoUser configuration not required (3)No
30(1)ANTSEL2OAntenna selection controlNoUser configuration not required (3)No
31RF_BGRFRF BG band: 2.4-GHz TX, RXN/AN/AN/A
32nRESETIMaster chip reset input. Active low input.N/AN/AN/A
33VDD_PA_INPowerInternal RF power amplifier (PA) input from PA DC/DC outputN/AN/AN/A
34SOP1IConfiguration sense-on-power 1N/AN/AN/A
35SOP0IConfiguration sense-on-power 0N/AN/AN/A
36LDO_IN1PowerInternal Analog RF supply from analog DC/DC outputN/AN/AN/A
37VIN_DCDC_ANAAnalog DC/DC supply input (same as battery voltage [VBAT])N/AN/AN/A
38DCDC_ANA_SWPowerInternal Analog DC/DC converter switching nodeN/AN/AN/A
39VIN_DCDC_PAPowerPA DC/DC converter input supply (same as battery voltage [VBAT])N/AN/AN/A
40DCDC_PA_SW_PPowerInternal PA DC/DC converter
+ve switching node		N/AN/AN/A
41DCDC_PA_SW_NPowerInternal PA DC/DC converter
–ve switching node		N/AN/AN/A
42DCDC_PA_OUTPowerInternal PA buck DC/DC converter outputN/AN/AN/A
43DCDC_DIG_SWPowerInternal Digital DC/DC converter switching nodeN/AN/AN/A
44VIN_DCDC_DIGPowerDigital DC/DC converter supply input (same as battery voltage [VBAT])N/AN/AN/A
45(4)DCDC_ANA2_SW_PI/OAnalog2 DC/DC converter
+ve switching node		NoUser configuration not required (3)No
46DCDC_ANA2_SW_NPowerInternal Analog2 DC/DC converter –ve switching nodeN/AN/AN/A
47VDD_ANA2PowerInternal Analog2 DC/DC outputN/AN/AN/A
48VDD_ANA1PowerInternal Analog1 power supply fed by analog2 DC/DC converter outputN/AN/AN/A
49VDD_RAMPowerInternal SRAM LDO outputN/AN/AN/A
50GPIO0I/OGeneral-purpose input or outputNoUser configuration not required (3)No
51RTC_XTAL_PAnalog32.768-kHz XTAL_P or external CMOS level clock inputN/AN/AN/A
52(5)RTC_XTAL_NAnalog32.768-kHz XTAL_NN/AUser configuration not required (3)(7)No
53GPIO30I/OGeneral-purpose input or outputNoUser configuration not required (3)No
54VIN_IO2Powerdevice supply voltage (VBAT)N/AN/AN/A
55GPIO1I/OGeneral-purpose input or outputNoNoNo
56VDD_DIG2Powerinternal digital core voltageN/AN/AN/A
57(6)GPIO2I/OAnalog input (up to 1.5-V ) or general-purpose input or outputYesSee (8)No
58(6)GPIO3I/OAnalog input (up to 1.5-V ) or general-purpose input or outputNoSee (8)No
59(6)GPIO4I/OAnalog input (up to 1.5-V ) or general-purpose input or outputYesSee (8)No
60(6)GPIO5I/OAnalog input (up to 1.5 V) or general-purpose input or outputNoSee (8)No
61GPIO6I/OGeneral-purpose input or outputNoNoNo
62GPIO7I/OGeneral-purpose input or outputNoNoNo
63GPIO8I/OGeneral-purpose input or outputNoNoNo
64GPIO9I/OGeneral-purpose input or outputNoNoNo
GND_TAB—Thermal pad and electrical groundN/AN/AN/A
(1) This pin is reserved for WLAN antenna selection, controlling an external RF switch that multiplexes the RF pin of the CC3220x device between two antennas. These pins must not be used for other functionalities.
(2) This pin has dual functions: as a SOP[2] (device operation mode), and as an external TCXO enable. As a TXCO enable, the pin is an output on power up and driven logic high. During hibernate low-power mode, the pin is in a Hi-Z state but is pulled down for SOP mode to disable TCXO. Because of the SOP functionality, the pin must be used as an output only.
(3) Device firmware automatically enables the digital path during ROM boot.
(4) Pin 45 is used by an internal DC/DC converter (ANA2_DCDC). This pin will be available automatically if the serial flash is forced in the CC3220SF device. For the CC3220R and CC3220S devices, pin 45 can be used as GPIO_31 if a supply is provided on pin 47.
(5) Pin 52 is used by the RTC crystal oscillator. These devices use automatic configuration sensing. Therefore, some board-level configuration is required to use pin 52 as a digital pad. Pin 52 is used for the RTC crystal in most applications. However, in some applications a 32.768-kHz square-wave clock might always be available onboard. When a 32.768-kHz square-wave clock is available, the crystal can be removed to free pin 52 for digital functions. The external clock must then be applied at pin 51. For the device to automatically detect this configuration, a 100-kΩ pullup resistor must be connected between pin 52 and the supply line. To prevent false detection, TI recommends using pin 52 for output-only functions.
(6) This pin is shared by the ADC inputs and digital I/O pad cells.
(7) To use the digital functions, RTC_XTAL_N must be pulled high to the supply voltage using a 100-kΩ resistor.
(8) Requires user configuration to enable the analog switch of the ADC channel (the switch is off by default.) The digital I/O is always connected and must be made Hi-Z before enabling the ADC switch.

 

Table 7-1 Pin Attributes
PIN NO.SIGNAL NAME(1)SIGNAL TYPE(2)PIN MUX ENCODINGSIGNAL DIRECTIONPAD STATES
LPDS(3)Hib(4)nRESET = 0
1GPIO10 (PN)I/O0I/OHi-Z, Pull, DriveHi-Z, Pull, DriveHi-Z
I2C_SCL1I/O (open drain)Hi-Z, Pull, Drive
GT_PWM063OHi-Z, Pull, Drive
UART1_TX7O1
SDCARD_CLK6O0
GT_CCP0112IHi-Z, Pull, Drive
2GPIO11 (PN)I/O0I/OHi-Z, Pull, DriveHi-Z, Pull, DriveHi-Z
I2C_SDA1I/O (open drain)Hi-Z, Pull, Drive
GT_PWM073OHi-Z, Pull, Drive
pXCLK (XVCLK)4O0
SDCARD_CMD6I/O (open drain)Hi-Z, Pull, Drive
UART1_RX7IHi-Z, Pull, Drive
GT_CCP0212IHi-Z, Pull, Drive
McAFSX13OHi-Z, Pull, Drive
3GPIO12 (PN)I/O0I/OHi-Z, Pull, DriveHi-Z, Pull, DriveHi-Z
McACLK3OHi-Z, Pull, Drive
pVS (VSYNC)4IHi-Z, Pull, Drive
I2C_SCL5I/O (open drain)Hi-Z, Pull, Drive
UART0_TX7O1
GT_CCP0312IHi-Z, Pull, Drive
4GPIO13 (PN)I/O0I/OHi-Z, Pull, DriveHi-Z, Pull, DriveHi-Z
I2C_SDA5I/O (open drain)
pHS (HSYNC)4I
UART0_RX7I
GT_CCP0412I
5GPIO14 (PN)I/O0I/OHi-Z, Pull, DriveHi-Z, Pull, DriveHi-Z
I2C_SCL5I/O (open drain)
GSPI_CLK7I/O
pDATA8 (CAM_D4)4I
GT_CCP0512I
6GPIO15 (PN)I/O0I/OHi-Z, Pull, DriveHi-Z, Pull, DriveHi-Z
I2C_SDA5I/O (open drain)
GSPI_MISO7I/O
pDATA9 (CAM_D5)4I
GT_CCP0613I
SDCARD_DATA08I/O
7GPIO16 (PN)I/O0I/OHi-Z, Pull, DriveHi-Z, Pull, DriveHi-Z
GSPI_MOSI7I/OHi-Z, Pull, Drive
pDATA10 (CAM_D6)4IHi-Z, Pull, Drive
UART1_TX5O1
GT_CCP0713IHi-Z, Pull, Drive
SDCARD_CLK8O0
8GPIO17 (PN)I/O0I/OHi-Z, Pull, DriveHi-Z, Pull, DriveHi-Z
UART1_RX5I
GSPI_CS7I/O
pDATA11 (CAM_D7)4I
SDCARD_CMD8I/O
9VDD_DIG1 (PN)—N/AN/AN/AN/AN/A
10VIN_IO1—N/AN/AN/AN/AN/A
11FLASH_SPI_CLKON/AOHi-Z, Pull, Drive(5)Hi-Z, Pull, DriveHi-Z
12FLASH_SPI_DOUTON/AOHi-Z, Pull, Drive(5)Hi-Z, Pull, DriveHi-Z
13FLASH_SPI_DININ/AIHi-Z, Pull, Drive(5)Hi-ZHi-Z
14FLASH_SPI_CSON/AO1Hi-Z, Pull, DriveHi-Z
15GPIO22 (PN)I/O0I/OHi-Z, Pull, DriveHi-Z, Pull, DriveHi-Z
McAFSXO7O
GT_CCP04I5I
16TDI (PN)I/O1IHi-Z, Pull, DriveHi-Z, Pull, DriveHi-Z
GPIO230I/O
UART1_TX2O1
I2C_SCL9I/O (open drain)Hi-Z, Pull, Drive
17TDO (PN)I/O1OHi-Z, Pull, DriveDriven high in SWD; driven low in 4-wire JTAGHi-Z
GPIO240I/O
PWM05O
UART1_RX2I
I2C_SDA9I/O (open drain)
GT_CCP064I
McAFSX6O
18GPIO28I/O0I/OHi-Z, Pull, DriveHi-Z, Pull, DriveHi-Z
19TCK (PN)I/O1IHi-Z, Pull, DriveHi-Z, Pull, DriveHi-Z
GT_PWM038O
20TMS (PN)I/O1I/OHi-Z, Pull, DriveHi-Z, Pull, DriveHi-Z
GPIO290
21(6)GPIO25O0OHi-Z, Pull, DriveDriven lowHi-Z
GT_PWM029OHi-Z, Pull, Drive
McAFSX2OHi-Z, Pull, Drive
TCXO_ENN/A
(see (8))		O0
SOP2 (PN)N/A
(see (9))		IHi-Z, Pull, Drive
22WLAN_XTAL_N—N/A
(see (8))		N/AN/AN/AN/A
23WLAN_XTAL_P—N/AN/AN/AN/AN/A
24VDD_PLL—N/AN/AN/AN/AN/A
25LDO_IN2—N/AN/AN/AN/AN/A
26NC—N/AN/AN/AN/AN/A
27NC—N/AN/AN/AN/AN/A
28NC—N/AN/AN/AN/AN/A
29(10)ANTSEL1O0OHi-Z, Pull, DriveHi-Z, Pull, DriveHi-Z
30(10)ANTSEL2O0OHi-Z, Pull, DriveHi-Z, Pull, DriveHi-Z
31RF_BG—N/AN/AN/AN/AN/A
32nRESET—N/AN/AN/AN/AN/A
33VDD_PA_IN—N/AN/AN/AN/AN/A
34SOP1—N/AN/AN/AN/AN/A
35SOP0—N/AN/AN/AN/AN/A
36LDO_IN1—N/AN/AN/AN/AN/A
37VIN_DCDC_ANA—N/AN/AN/AN/AN/A
38DCDC_ANA_SW—N/AN/AN/AN/AN/A
39VIN_DCDC_PA—N/AN/AN/AN/AN/A
40DCDC_PA_SW_P—N/AN/AN/AN/AN/A
41DCDC_PA_SW_N—N/AN/AN/AN/AN/A
42DCDC_PA_OUT—N/AN/AN/AN/AN/A
43DCDC_DIG_SW—N/AN/AN/AN/AN/A
44VIN_DCDC_DIG—N/AN/AN/AN/AN/A
45(7)GPIO31I/O0I/OHi-ZHi-ZHi-Z
UART0_RX9I
McAFSX12O
UART1_RX2I
McAXR06I/O
GSPI_CLK7I/O
DCDC_ANA2_SW_P (PN)—N/A
(see (8))		N/AN/AN/AN/A
46DCDC_ANA2_SW_N—N/AN/AN/AN/AN/A
47VDD_ANA2—N/AN/AN/AN/AN/A
48VDD_ANA1—N/AN/AN/AN/AN/A
49VDD_RAM—N/AN/AN/AN/AN/A
50GPIO0 (PN)I/O0I/OHi-Z, Pull, DriveHi-Z, Pull, DriveHi-Z
UART0_CTS12IHi-Z, Pull, Drive
McAXR16I/OHi-Z, Pull, Drive
GT_CCP007IHi-Z, Pull, Drive
GSPI_CS9I/OHi-Z, Pull, Drive
UART1_RTS10O1
UART0_RTS3O1
McAXR04I/OHi-Z, Pull, Drive
51RTC_XTAL_P—N/AN/AN/AN/AN/A
52(11)RTC_XTAL_N (PN)ON/AN/AN/AHi-Z, Pull, DriveHi-Z
GPIO320OHi-Z, Pull, Drive
McACLK2O
McAXR04O
UART0_RTS6O1
GSPI_MOSI8OHi-Z, Pull, Drive
53GPIO30 (PN)I/O0I/OHi-Z, Pull, DriveHi-Z, Pull, DriveHi-Z
UART0_TX9O1
McACLK2OHi-Z, Pull, Drive
McAFSX3O
GT_CCP054I
GSPI_MISO7I/O
54VIN_IO2—N/AN/AN/AN/AN/A
55GPIO1 (PN)I/O0I/OHi-Z, Pull, DriveHi-Z, Pull, DriveHi-Z
UART0_TX3O1
pCLK (PIXCLK)4IHi-Z, Pull, Drive
UART1_TX6O1
GT_CCP017IHi-Z, Pull, Drive
56VDD_DIG2—N/AN/AN/AN/AN/A
57(12)ADC_CH0Analog input (up to 1.5 V) or digital I/ON/A
(see (8))		IHi-Z, Pull, DriveHi-Z, Pull, DriveHi-Z
GPIO2 (PN)0I/O
UART0_RX3I
UART1_RX6I
GT_CCP027I
58(12)ADC_CH1Analog input (up to 1.5 V) or digital I/ON/A
(see (8))		IHi-Z, Pull, DriveHi-Z, Pull, DriveHi-Z
GPIO3 (PN)0I/O
UART1_TX6O1
pDATA7 (CAM_D3)4IHi-Z, Pull, Drive
59(12)ADC_CH2Analog input (up to 1.5 V) or digital I/ON/A
(see (8))		IHi-Z, Pull, DriveHi-Z, Pull, DriveHi-Z
GPIO4 (PN)0I/O
UART1_RX6I
pDATA6 (CAM_D2)4I
60(12)ADC_CH3Analog input (up to 1.5 V) or digital I/ON/A
(see (8))		IHi-Z, Pull, DriveHi-Z, Pull, DriveHi-Z
GPIO5 (PN)0I/O
pDATA5 (CAM_D1)4I
McAXR16I/O
GT_CCP057I
61GPIO6 (PN)I/O0I/OHi-Z, Pull, DriveHi-Z, Pull, DriveHi-Z
UART0_RTS5O1
pDATA4 (CAM_D0)4IHi-Z, Pull, Drive
UART1_CTS3I
UART0_CTS6I
GT_CCP067I
62GPIO7 (PN)I/O0I/OHi-Z, Pull, DriveHi-Z, Pull, DriveHi-Z
McACLKX13O
UART1_RTS3O1
UART0_RTS10O
UART0_TX11O
63GPIO8 (PN)I/O0I/OHi-Z, Pull, DriveHi-Z, Pull, DriveHi-Z
SDCARD_IRQ6I
McAFSX7O
GT_CCP0612I
64GPIO9 (PN)I/O0I/OHi-Z, Pull, DriveHi-Z, Pull, DriveHi-Z
GT_PWM053O
SDCARD_DATA06I/O
McAXR07I/O
GT_CCP0012I
GND_TAB—N/AN/AN/AN/AN/A
(1) Signals names with (PN) denote the default pin name.
(2) Signal Types: I = Input, O = Output, I/O = Input or Output.
(3) LPDS state: Unused I/Os are in a Hi-Z state. Software may program the I/Os to be input with pull or drive (regardless of active pin configuration), according to the need.
(4) Hibernate mode: The I/Os are in a Hi-Z state. Software may program the I/Os to be input with pull or drive (regardless of active pin configuration), according to the need.
(5) To minimize leakage in some serial flash vendors during LPDS, TI recommends that the user application always enables internal weak pulldown resistors on the FLASH_SPI_DIN, FLASH_SPI_DOUT, and FLASH_SPI_CLK pins.
(6) This pin has dual functions: as a SOP[2] (device operation mode), and as an external TCXO enable. As a TXCO enable, the pin is an output on power up and driven logic high. During hibernate low-power mode, the pin is in a Hi-Z state but is pulled down for SOP mode to disable TCXO. Because of the SOP functionality, the pin must be used as an output only.
(7) Pin 45 is used by an internal DC/DC (ANA2_DCDC). This pin will be available automatically if serial flash is forced in the CC3220SF device. For the CC3220R and CC3220S devices, pin 45 can be used as GPIO_31 if a supply is provided on pin 47.
(8) For details on proper use, see Section 7.5.
(9) This pin is one of three that must have a passive pullup or pulldown resistor onboard to configure the device hardware power-up mode. For this reason, the pin must be output only when used for digital functions.
(10) This pin is reserved for WLAN antenna selection, controlling an external RF switch that multiplexes the RF pin of the CC3220x device between two antennas. These pins must not be used for other functionalities.
(11) Pin 52 is used by the RTC crystal oscillator. These devices use automatic configuration sensing. Therefore, some board-level configuration is required to use pin 52 as a digital pad. Pin 52 is used for RTC crystal in most applications. However, in some applications a 32.768-kHz square-wave clock might always be available onboard. When a 32.768-kHz square-wave clock is available, the crystal can be removed to free pin 52 for digital functions. The external clock must then be applied at pin 51. For the chip to automatically detect this configuration, a 100-kΩ pullup resistor must be connected between pin 52 and the supply line. To prevent false detection, TI recommends using pin 52 for output-only functions.
(12) This pin is shared by the ADC inputs and digital I/O pad cells.

 

Note:

The ADC inputs are tolerant up to 1.8 V (see Section 8.14.6.6.1 for more details about the usable range of the ADC). On the other hand, the digital pads can tolerate up to 3.6 V. Hence, take care to prevent accidental damage to the ADC inputs. TI recommends first disabling the output buffers of the digital I/Os corresponding to the desired ADC channel (that is, converted to Hi-Z state), and thereafter disabling the respective pass switches (S7 [Pin 57], S8 [Pin 58], S9 [Pin 59], and S10 [Pin 60]). For more information about drive strength and reset states for analog-digital multiplexed pins, see Section 7.5.