JAJSGL1C September   2016  – May 2021 CC3220R , CC3220S , CC3220SF

PRODUCTION DATA  

  1. 特長
  2. アプリケーション
  3. 概要
  4. 機能ブロック図
  5. Revision History
  6. Device Comparison
    1. 6.1 Related Products
  7. Terminal Configuration and Functions
    1. 7.1 Pin Diagram
    2. 7.2 Pin Attributes and Pin Multiplexing
      1. 7.2.1 Pin Descriptions
    3. 7.3 Signal Descriptions
      1. 7.3.1 Signal Descriptions
    4. 7.4 Pin Multiplexing
    5. 7.5 Drive Strength and Reset States for Analog and Digital Multiplexed Pins
    6. 7.6 Pad State After Application of Power to Chip But Before Reset Release
    7. 7.7 Connections for Unused Pins
  8. Specifications
    1. 8.1  Absolute Maximum Ratings
    2. 8.2  ESD Ratings
    3. 8.3  Power-On Hours (POH)
    4. 8.4  Recommended Operating Conditions
    5. 8.5  Current Consumption Summary (CC3220R, CC3220S)
    6. 8.6  Current Consumption Summary (CC3220SF)
    7. 8.7  TX Power and IBAT versus TX Power Level Settings
    8. 8.8  Brownout and Blackout Conditions
    9. 8.9  Electrical Characteristics (3.3 V, 25°C)
    10. 8.10 WLAN Receiver Characteristics
    11. 8.11 WLAN Transmitter Characteristics
    12. 8.12 WLAN Filter Requirements
      1. 8.12.1 WLAN Filter Requirements
    13. 8.13 Thermal Resistance Characteristics
      1. 8.13.1 Thermal Resistance Characteristics for RGK Package
    14. 8.14 Timing and Switching Characteristics
      1. 8.14.1 Power Supply Sequencing
      2. 8.14.2 Device Reset
      3. 8.14.3 Reset Timing
        1. 8.14.3.1 nRESET (32-kHz Crystal)
        2. 8.14.3.2 First-Time Power-Up and Reset Removal Timing Requirements (32-kHz Crystal)
        3. 8.14.3.3 nRESET (External 32-kHz)
          1. 8.14.3.3.1 First-Time Power-Up and Reset Removal Timing Requirements (External 32-kHz)
      4. 8.14.4 Wakeup From HIBERNATE Mode
      5. 8.14.5 Clock Specifications
        1. 8.14.5.1 Slow Clock Using Internal Oscillator
          1. 8.14.5.1.1 RTC Crystal Requirements
        2. 8.14.5.2 Slow Clock Using an External Clock
          1. 8.14.5.2.1 External RTC Digital Clock Requirements
        3. 8.14.5.3 Fast Clock (Fref) Using an External Crystal
          1. 8.14.5.3.1 WLAN Fast-Clock Crystal Requirements
        4. 8.14.5.4 Fast Clock (Fref) Using an External Oscillator
          1. 8.14.5.4.1 External Fref Clock Requirements (–40°C to +85°C)
      6. 8.14.6 Peripherals Timing
        1. 8.14.6.1  SPI
          1. 8.14.6.1.1 SPI Master
            1. 8.14.6.1.1.1 SPI Master Timing Parameters
          2. 8.14.6.1.2 SPI Slave
            1. 8.14.6.1.2.1 SPI Slave Timing Parameters
        2. 8.14.6.2  I2S
          1. 8.14.6.2.1 I2S Transmit Mode
            1. 8.14.6.2.1.1 I2S Transmit Mode Timing Parameters
          2. 8.14.6.2.2 I2S Receive Mode
            1. 8.14.6.2.2.1 I2S Receive Mode Timing Parameters
        3. 8.14.6.3  GPIOs
          1. 8.14.6.3.1 GPIO Output Transition Time Parameters (Vsupply = 3.3 V)
            1. 8.14.6.3.1.1 GPIO Output Transition Times (Vsupply = 3.3 V) (1) (1)
          2. 8.14.6.3.2 GPIO Output Transition Time Parameters (Vsupply = 1.85 V)
            1. 8.14.6.3.2.1 GPIO Output Transition Times (Vsupply = 1.85 V) (1) (1)
          3. 8.14.6.3.3 GPIO Input Transition Time Parameters
            1. 8.14.6.3.3.1 GPIO Input Transition Time Parameters'
        4. 8.14.6.4  I2C
          1. 8.14.6.4.1 I2C Timing Parameters (1)
        5. 8.14.6.5  IEEE 1149.1 JTAG
          1. 8.14.6.5.1 JTAG Timing Parameters
        6. 8.14.6.6  ADC
          1. 8.14.6.6.1 ADC Electrical Specifications
        7. 8.14.6.7  Camera Parallel Port
          1. 8.14.6.7.1 Camera Parallel Port Timing Parameters
        8. 8.14.6.8  UART
        9. 8.14.6.9  SD Host
        10. 8.14.6.10 Timers
  9. Detailed Description
    1. 9.1 Arm® Cortex®-M4 Processor Core Subsystem
    2. 9.2 Wi-Fi Network Processor Subsystem
      1. 9.2.1 WLAN
      2. 9.2.2 Network Stack
    3. 9.3 Security
    4. 9.4 Power-Management Subsystem
      1. 9.4.1 VBAT Wide-Voltage Connection
      2. 9.4.2 Preregulated 1.85-V Connection
    5. 9.5 Low-Power Operating Mode
    6. 9.6 Memory
      1. 9.6.1 External Memory Requirements
      2. 9.6.2 Internal Memory
        1. 9.6.2.1 SRAM
        2. 9.6.2.2 ROM
        3. 9.6.2.3 Flash Memory
        4. 9.6.2.4 Memory Map
    7. 9.7 Restoring Factory Default Configuration
    8. 9.8 Boot Modes
      1. 9.8.1 Boot Mode List
  10. 10Applications, Implementation, and Layout
    1. 10.1 Application Information
      1. 10.1.1 Typical Application —CC3220x Wide-Voltage Mode
      2. 10.1.2 Typical Application Schematic—CC3220x Preregulated, 1.85-V Mode
    2. 10.2 PCB Layout Guidelines
      1. 10.2.1 General PCB Guidelines
      2. 10.2.2 Power Layout and Routing
        1. 10.2.2.1 Design Considerations
      3. 10.2.3 Clock Interfaces
      4. 10.2.4 Digital Input and Output
      5. 10.2.5 RF Interface
  11. 11Device and Documentation Support
    1. 11.1 Development Tools and Software
    2. 11.2 Firmware Updates
    3. 11.3 Device Nomenclature
    4. 11.4 Documentation Support
    5. 11.5 サポート・リソース
    6. 11.6 Trademarks
    7. 11.7 Electrostatic Discharge Caution
    8. 11.8 Export Control Notice
    9. 11.9 Glossary
  12. 12Mechanical, Packaging, and Orderable Information
    1. 12.1 Packaging Information

パッケージ・オプション

メカニカル・データ(パッケージ|ピン)
サーマルパッド・メカニカル・データ
発注情報

Signal Descriptions

FUNCTIONSIGNAL NAMEPIN
NO.
PIN
TYPE
SIGNAL DIRECTIONDESCRIPTION
ADCADC_CH057I/OIADC channel 0 input (maximum of 1.5 V)
ADC_CH158I/OIADC channel 1 input (maximum of 1.5 V)
ADC_CH259I/OIADC channel 2 input (maximum of 1.5 V)
ADC_CH360I/OIADC channel 3 input (maximum of 1.5 V)
Antenna selectionANTSEL129OOAntenna selection control 1
ANTSEL230OOAntenna selection control 2
ClockTCX0_EN21OOEnable to optional external 40-MHz TCXO
WLAN_XTAL_N2240-MHz crystal; pull down if external TCXO is used
WLAN_XTAL_P2340-MHz crystal or TCXO clock input
RTC_XTAL_P51Connect 32.768-kHz crystal or force external CMOS level clock
RTC_XTAL_N52Connect 32.768-kHz crystal or connect 100-kΩ resistor to supply voltage
JTAG / SWDTDI16I/OIJTAG TDI. Reset default pinout.
TDO17I/OOJTAG TDO. Reset default pinout.
TCK19I/OIJTAG/SWD TCK. Reset default pinout.
TMS20I/OI/OJTAG/SWD TMS. Reset default pinout.
I2CI2C_SCL1I/OI/O (open drain)I2C clock data
3
5
16
I2C_SDA2I/OI/O (open drain)I2C data
4
6
17
TimersGT_PWM061I/OOPulse-width modulated O/P
GT_CCP011I/OITimer capture port
GT_PWM072I/OOPulse-width modulated O/P
GT_CCP022I/OITimer capture port
GT_CCP033I/OI
GT_CCP044I/OI
15I/OI
GT_CCP055I/OI
GT_CCP066I/OI
17I/OI
61I/OI
63I/OI
GT_CCP077I/OI
PWM017I/OOPulse-width modulated output
GT_PWM0319I/OO
GT_PWM0221OO
GT_CCP0050I/OITimer capture port
64I/OI
GT_CCP0553I/OI
GT_CCP0155I/OI
GT_CCP0257I/OI
GT_CCP0560II
GT_PWM0564I/OOPulse-width modulated output
GPIOGPIO101I/OI/OGeneral-purpose input or output
GPIO112I/OI/O
GPIO123I/OI/O
GPIO134I/OI/O
GPIO145I/OI/O
GPIO156I/OI/O
GPIO167I/OI/O
GPIO178I/OI/O
GPIO2215I/OI/O
GPIO2316I/OI/O
GPIO2417I/OI/O
GPIO2818I/OI/O
GPIO2920I/OI/O
GPIO2521OOGeneral-purpose output only
GPIO3145I/OI/OGeneral-purpose input or output
GPIO050I/OI/O
GPIO3252I/OOGeneral-purpose output only
GPIO3053I/OI/OGeneral-purpose input or output
GPIO155I/OI/O
GPIO257I/OI/O
GPIO358I/OI/O
GPIO459I/OI/O
GPIO560I/OI/O
GPIO661I/OI/O
GPIO762I/OI/O
GPIO863I/OI/O
GPIO964I/OI/O
McASP
I2S or PCM
McAFSX2I/OOI2S audio port frame sync
15
17
21
45
53
63
McACLK3I/OOI2S audio port clock output
52OO
53I/OO
McAXR150I/OI/OI2S audio port data 1 (RX and TX)
60II/O
McAXR045I/OI/OI2S audio port data 0 (RX and TX)
50I/OI/O
52OOI2S audio port data (only output mode is supported on pin 52)
64I/OI/OI2S audio port data (RX and TX)
McACLKX62I/OOI2S audio port clock
Multimedia card
(MMC or SD)
SDCARD_CLK1I/OOSD card clock data
7
SDCARD_CMD2I/OI/O (open drain)SD card command line
8I/OI/O
SDCARD_DATA06I/OI/OSD card data
64
SDCARD_IRQ63I/OIInterrupt from SD card (future support)
Parallel interface
(8-bit π)
pXCLK (XVCLK)2I/OOFree clock to parallel camera
pVS (VSYNC)3I/OIParallel camera vertical sync
pHS (HSYNC)4I/OIParallel camera horizontal sync
pDATA8 (CAM_D4)5I/OIParallel camera data bit 4
pDATA9 (CAM_D5)6I/OIParallel camera data bit 5
pDATA10 (CAM_D6)7I/OIParallel camera data bit 6
pDATA11 (CAM_D7)8I/OIParallel camera data bit 7
pCLK (PIXCLK)55I/OIPixel clock from parallel camera sensor
pDATA7 (CAM_D3)58I/OIParallel camera data bit 3
pDATA6 (CAM_D2)59I/OIParallel camera data bit 2
pDATA5 (CAM_D1)60IIParallel camera data bit 1
pDATA4 (CAM_D0)61I/OIParallel camera data bit 0
PowerVDD_DIG19Internal digital core voltage
VIN_IO110Device supply voltage (VBAT)
VDD_PLL24Internal analog voltage
LDO_IN225Internal analog RF supply from analog DC/DC output
VDD_PA_IN33Internal PA supply voltage from PA DC/DC output
LDO_IN136Internal analog RF supply from analog DC/DC output
VIN_DCDC_ANA37Analog DC/DC input (connected to device input supply [VBAT])
DCDC_ANA_SW38Internal analog DC/DC switching node
VIN_DCDC_PA39PA DC/DC input (connected to device input supply [VBAT])
DCDC_PA_SW_P40Internal PA DC/DC switching node
DCDC_PA_SW_N41
DCDC_PA_OUT42Internal PA buck converter output
DCDC_DIG_SW43Internal digital DC/DC switching node
VIN_DCDC_DIG44Digital DC/DC input (connected to device input supply [VBAT])
DCDC_ANA2_SW_P45Analog to DC/DC converter +ve switching node
DCDC_ANA2_SW_N46Internal analog to DC/DC converter –ve switching node
VDD_ANA247Internal analog to DC/DC output
VDD_ANA148Internal analog supply fed by ANA2 DC/DC output
VDD_RAM49Internal SRAM LDO output
VIN_IO254Device supply voltage (VBAT)
VDD_DIG256Internal digital core voltage
SPIGSPI_CLK5I/OI/OGeneral SPI clock
45I/OI/O
GSPI_MISO6I/OI/OGeneral SPI MISO
53I/OI/O
GSPI_CS8I/OI/OGeneral SPI chip select
50I/OI/O
GSPI_MOSI7I/OI/OGeneral SPI MOSI
52OO
FLASH SPIFLASH_SPI_CLK11OOClock to SPI serial flash (fixed default)
FLASH_SPI_DOUT12OOData to SPI serial flash (fixed default)
FLASH_SPI_DIN13IIData from SPI serial flash (fixed default)
FLASH_SPI_CS14OODevice select to SPI serial flash (fixed default)
UARTUART1_TX1I/OOUART1 TX data
7I/OO
16I/OO
55I/OO
58I/OO
UART1_RX2I/OIUART1 RX data
8I/OI
17I/OI
45I/OI
57I/OI
59I/OI
UART1_RTS50I/OOUART1 request-to-send (active low)
62I/OO
UART1_CTS61I/OIUART1 clear-to-send (active low)
UART0_TX3I/OOUART0 TX data
53I/OO
55I/OO
62I/OO
UART0_RX4I/OIUART0 RX data
45I/OI
57I/OI
UART0_CTS50I/OIUART0 clear-to-send input (active low)
61I/OI
UART0_RTS50I/OOUART0 request-to-send (active low)
52OO
61I/OO
62I/OO
Sense-on-PowerSOP221(1)OISense-on-power 2
SOP134Configuration sense-on-power 1
SOP035Configuration sense-on-power 0
ResetnRESET32Global master device reset (active low)
RFRF_BG31WLAN analog RF 802.11 b/g bands
This pin has dual functions: as a SOP[2] (device operation mode), and as an external TCXO enable. As a TXCO enable, the pin is an output on power up and driven logic high. During hibernate low-power mode, the pin is in a Hi-Z state but is pulled down for SOP mode to disable TCXO. Because of the SOP functionality, the pin must be used as an output only.