JAJSGL1 データシート

JAJSGL1C September 2016 – May 2021 CC3220R , CC3220S , CC3220SF

PRODUCTION DATA

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）

RGK|64
- MPQF273C

サーマルパッド・メカニカル・データ

RGK|64
- QFND565B

発注情報

7.3.1 Signal Descriptions

FUNCTION	SIGNAL NAME	PIN NO.	PIN TYPE	SIGNAL DIRECTION	DESCRIPTION
ADC	ADC_CH0	57	I/O	I	ADC channel 0 input (maximum of 1.5 V)
	ADC_CH1	58	I/O	I	ADC channel 1 input (maximum of 1.5 V)
	ADC_CH2	59	I/O	I	ADC channel 2 input (maximum of 1.5 V)
	ADC_CH3	60	I/O	I	ADC channel 3 input (maximum of 1.5 V)
Antenna selection	ANTSEL1	29	O	O	Antenna selection control 1
Antenna selection	ANTSEL2	30	O	O	Antenna selection control 2
Clock	TCX0_EN	21	O	O	Enable to optional external 40-MHz TCXO
	WLAN_XTAL_N	22	—	—	40-MHz crystal; pull down if external TCXO is used
	WLAN_XTAL_P	23	—	—	40-MHz crystal or TCXO clock input
	RTC_XTAL_P	51	—	—	Connect 32.768-kHz crystal or force external CMOS level clock
	RTC_XTAL_N	52	—	—	Connect 32.768-kHz crystal or connect 100-kΩ resistor to supply voltage
JTAG / SWD	TDI	16	I/O	I	JTAG TDI. Reset default pinout.
	TDO	17	I/O	O	JTAG TDO. Reset default pinout.
	TCK	19	I/O	I	JTAG/SWD TCK. Reset default pinout.
	TMS	20	I/O	I/O	JTAG/SWD TMS. Reset default pinout.
I²C	I2C_SCL	1	I/O	I/O (open drain)	I²C clock data
		3
		5
		16
	I2C_SDA	2	I/O	I/O (open drain)	I²C data
		4
		6
		17
Timers	GT_PWM06	1	I/O	O	Pulse-width modulated O/P
	GT_CCP01	1	I/O	I	Timer capture port
	GT_PWM07	2	I/O	O	Pulse-width modulated O/P
	GT_CCP02	2	I/O	I	Timer capture port
	GT_CCP03	3	I/O	I
	GT_CCP04	4	I/O	I
	GT_CCP04	15	I/O	I
	GT_CCP05	5	I/O	I
	GT_CCP06	6	I/O	I
		17	I/O	I
		61	I/O	I
		63	I/O	I
	GT_CCP07	7	I/O	I
	PWM0	17	I/O	O	Pulse-width modulated output
	GT_PWM03	19	I/O	O
	GT_PWM02	21	O	O
	GT_CCP00	50	I/O	I	Timer capture port
	GT_CCP00	64	I/O	I
	GT_CCP05	53	I/O	I
	GT_CCP01	55	I/O	I
	GT_CCP02	57	I/O	I
	GT_CCP05	60	I	I
	GT_PWM05	64	I/O	O	Pulse-width modulated output
GPIO	GPIO10	1	I/O	I/O	General-purpose input or output
	GPIO11	2	I/O	I/O
	GPIO12	3	I/O	I/O
	GPIO13	4	I/O	I/O
	GPIO14	5	I/O	I/O
	GPIO15	6	I/O	I/O
	GPIO16	7	I/O	I/O
	GPIO17	8	I/O	I/O
	GPIO22	15	I/O	I/O
	GPIO23	16	I/O	I/O
	GPIO24	17	I/O	I/O
	GPIO28	18	I/O	I/O
	GPIO29	20	I/O	I/O
	GPIO25	21	O	O	General-purpose output only
	GPIO31	45	I/O	I/O	General-purpose input or output
	GPIO0	50	I/O	I/O	General-purpose input or output
	GPIO32	52	I/O	O	General-purpose output only
	GPIO30	53	I/O	I/O	General-purpose input or output
	GPIO1	55	I/O	I/O
	GPIO2	57	I/O	I/O
	GPIO3	58	I/O	I/O
	GPIO4	59	I/O	I/O
	GPIO5	60	I/O	I/O
	GPIO6	61	I/O	I/O
	GPIO7	62	I/O	I/O
	GPIO8	63	I/O	I/O
	GPIO9	64	I/O	I/O
McASP I²S or PCM	McAFSX	2	I/O	O	I²S audio port frame sync
		15
		17
		21
		45
		53
		63
	McACLK	3	I/O	O	I²S audio port clock output
		52	O	O
		53	I/O	O
	McAXR1	50	I/O	I/O	I²S audio port data 1 (RX and TX)
	McAXR1	60	I	I/O	I²S audio port data 1 (RX and TX)
	McAXR0	45	I/O	I/O	I²S audio port data 0 (RX and TX)
		50	I/O	I/O	I²S audio port data 0 (RX and TX)
		52	O	O	I²S audio port data (only output mode is supported on pin 52)
		64	I/O	I/O	I²S audio port data (RX and TX)
	McACLKX	62	I/O	O	I²S audio port clock
Multimedia card (MMC or SD)	SDCARD_CLK	1	I/O	O	SD card clock data
	SDCARD_CLK	7	I/O	O	SD card clock data
	SDCARD_CMD	2	I/O	I/O (open drain)	SD card command line
	SDCARD_CMD	8	I/O	I/O	SD card command line
	SDCARD_DATA0	6	I/O	I/O	SD card data
	SDCARD_DATA0	64	I/O	I/O	SD card data
	SDCARD_IRQ	63	I/O	I	Interrupt from SD card (future support)
Parallel interface (8-bit π)	pXCLK (XVCLK)	2	I/O	O	Free clock to parallel camera
	pVS (VSYNC)	3	I/O	I	Parallel camera vertical sync
	pHS (HSYNC)	4	I/O	I	Parallel camera horizontal sync
	pDATA8 (CAM_D4)	5	I/O	I	Parallel camera data bit 4
	pDATA9 (CAM_D5)	6	I/O	I	Parallel camera data bit 5
	pDATA10 (CAM_D6)	7	I/O	I	Parallel camera data bit 6
	pDATA11 (CAM_D7)	8	I/O	I	Parallel camera data bit 7
	pCLK (PIXCLK)	55	I/O	I	Pixel clock from parallel camera sensor
	pDATA7 (CAM_D3)	58	I/O	I	Parallel camera data bit 3
	pDATA6 (CAM_D2)	59	I/O	I	Parallel camera data bit 2
	pDATA5 (CAM_D1)	60	I	I	Parallel camera data bit 1
	pDATA4 (CAM_D0)	61	I/O	I	Parallel camera data bit 0
Power	VDD_DIG1	9	—	—	Internal digital core voltage
	VIN_IO1	10	—	—	Device supply voltage (V_BAT)
	VDD_PLL	24	—	—	Internal analog voltage
	LDO_IN2	25	—	—	Internal analog RF supply from analog DC/DC output
	VDD_PA_IN	33	—	—	Internal PA supply voltage from PA DC/DC output
	LDO_IN1	36	—	—	Internal analog RF supply from analog DC/DC output
	VIN_DCDC_ANA	37	—	—	Analog DC/DC input (connected to device input supply [V_BAT])
	DCDC_ANA_SW	38	—	—	Internal analog DC/DC switching node
	VIN_DCDC_PA	39	—	—	PA DC/DC input (connected to device input supply [V_BAT])
	DCDC_PA_SW_P	40	—	—	Internal PA DC/DC switching node
	DCDC_PA_SW_N	41	—	—	Internal PA DC/DC switching node
	DCDC_PA_OUT	42	—	—	Internal PA buck converter output
	DCDC_DIG_SW	43	—	—	Internal digital DC/DC switching node
	VIN_DCDC_DIG	44	—	—	Digital DC/DC input (connected to device input supply [V_BAT])
	DCDC_ANA2_SW_P	45	—	—	Analog to DC/DC converter +ve switching node
	DCDC_ANA2_SW_N	46	—	—	Internal analog to DC/DC converter –ve switching node
	VDD_ANA2	47	—	—	Internal analog to DC/DC output
	VDD_ANA1	48	—	—	Internal analog supply fed by ANA2 DC/DC output
	VDD_RAM	49	—	—	Internal SRAM LDO output
	VIN_IO2	54	—	—	Device supply voltage (V_BAT)
	VDD_DIG2	56	—	—	Internal digital core voltage
SPI	GSPI_CLK	5	I/O	I/O	General SPI clock
	GSPI_CLK	45	I/O	I/O	General SPI clock
	GSPI_MISO	6	I/O	I/O	General SPI MISO
	GSPI_MISO	53	I/O	I/O	General SPI MISO
	GSPI_CS	8	I/O	I/O	General SPI chip select
	GSPI_CS	50	I/O	I/O	General SPI chip select
	GSPI_MOSI	7	I/O	I/O	General SPI MOSI
	GSPI_MOSI	52	O	O	General SPI MOSI
FLASH SPI	FLASH_SPI_CLK	11	O	O	Clock to SPI serial flash (fixed default)
	FLASH_SPI_DOUT	12	O	O	Data to SPI serial flash (fixed default)
	FLASH_SPI_DIN	13	I	I	Data from SPI serial flash (fixed default)
	FLASH_SPI_CS	14	O	O	Device select to SPI serial flash (fixed default)
UART	UART1_TX	1	I/O	O	UART1 TX data
		7	I/O	O
		16	I/O	O
		55	I/O	O
		58	I/O	O
	UART1_RX	2	I/O	I	UART1 RX data
		8	I/O	I
		17	I/O	I
		45	I/O	I
		57	I/O	I
		59	I/O	I
	UART1_RTS	50	I/O	O	UART1 request-to-send (active low)
	UART1_RTS	62	I/O	O	UART1 request-to-send (active low)
	UART1_CTS	61	I/O	I	UART1 clear-to-send (active low)
	UART0_TX	3	I/O	O	UART0 TX data
		53	I/O	O
		55	I/O	O
		62	I/O	O
	UART0_RX	4	I/O	I	UART0 RX data
		45	I/O	I
		57	I/O	I
	UART0_CTS	50	I/O	I	UART0 clear-to-send input (active low)
	UART0_CTS	61	I/O	I	UART0 clear-to-send input (active low)
	UART0_RTS	50	I/O	O	UART0 request-to-send (active low)
		52	O	O
		61	I/O	O
		62	I/O	O
Sense-on-Power	SOP2	21⁽¹⁾	O	I	Sense-on-power 2
	SOP1	34	—	—	Configuration sense-on-power 1
	SOP0	35	—	—	Configuration sense-on-power 0
Reset	nRESET	32	—	—	Global master device reset (active low)
RF	RF_BG	31	—	—	WLAN analog RF 802.11 b/g bands

(1) This pin has dual functions: as a SOP[2] (device operation mode), and as an external TCXO enable. As a TXCO enable, the pin is an output on power up and driven logic high. During hibernate low-power mode, the pin is in a Hi-Z state but is pulled down for SOP mode to disable TCXO. Because of the SOP functionality, the pin must be used as an output only.