JAJSRA0 データシート

JAJSRA0D March 2023 – December 2023 CC3300 , CC3301

PRODUCTION DATA

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）

RSB|40
- MPQF185C

サーマルパッド・メカニカル・データ

RSB|40
- QFND094M

発注情報

5.2 Pin Attributes

Table 5-1 Pin Attributes

PIN	SIGNAL NAME	TYPE	DIR (I/O)	VOLTAGE LEVEL	SHUTDOWN STATE	STATE AFTER POWER-UP	DESCRIPTION
1	PA_LDO_OUT	Analog					RF power amplifier LDO output
2	RF_BG	RF	I/O				Bluetooth Low Energy and WLAN 2.4-GHz RF port
3	GND	GND					GND
4	VDDA_IN1	POW					1.8 V supply for analog domain
5	VDDA_IN2	POW					1.8 V supply for analog domain
6	HFXT_P	Analog		Sine			XTAL_P
7	HFXT_M	Analog					XTAL_N
8	COEX_GRANT²	Digital	O	V_IO	PD	PD	External coexistence interface - grant
9	COEX_PRIORITY²	Digital	I	V_IO	PU	PU	External coexistence interface - priority
10	COEX_REQ²	Digital	I	V_IO	PU	PU	External coexistence interface - request
11	UART RTS	Digital	O	V_IO	PU	PU	Device RTS signal - flow control for BLE HCI
12	UART CTS	Digital	I	V_IO	PU	PU	Device CTS signal - flow control for BLE HCI
13	UART RX	Digital	I	V_IO	PU	PU	UART RX for BLE HCI
14	UART TX	Digital	O	V_IO	PU	PU	UART TX for BLE HCI
15	ANT_SEL²	Digital	O	V_IO	PD	PD	Antenna select control line
16	GND	GND					GND
17	VIO	POW					1.8 V IO supply
18	SDIO CMD	Digital	I/O	V_IO	HiZ	HiZ	SDIO command or SPI PICO
19	SDIO CLK	Digital	I	V_IO	HiZ	HiZ	SDIO clock or SPI clock
20	GND	GND					GND
21	SDIO D3	Digital	I/O	V_IO	HiZ	PU	SDIO data D3 or SPI CS
22	SDIO D2	Digital	I/O	V_IO	HiZ	HiZ	SDIO data D2
23	SDIO D1	Digital	I/O	V_IO	HiZ	HiZ	SDIO data D1
24	SDIO D0	Digital	I/O	V_IO	HiZ	HiZ	SDIO data D0 or SPI POCI
25	GND	GND					GND
26	SWCLK	Digital	I	V_IO	PD	PD	Serial wire debug clock
27	SWDIO	Digital	I/O	V_IO	PU	PU	Serial wire debug I/O
28	LOGGER³	Digital	O	V_IO	PU	PU	Tracer (UART TX debug logger)
29	HOST_IRQ_WL³	Digital	O	V_IO	PD	0	Interrupt request to host for WLAN
30	HOST_IRQ_BLE³	Digital	O	V_IO	PD	PD	Interrupt request to host for BLE (in shared SDIO mode)
31	DIG_LDO_OUT	Analog	O				Digital LDO output to decoupling capacitor
32	VDD_MAIN_IN	POW					1.8 V supply input for SRAM and digital
33	nRESET	Digital	I	V_IO	PD	PD	Reset line for enabling or disabling device (active low)
34	SLOW_CLK_IN	Digital	I	V_IO	PD	PD	32.768-kHz RTC clock input
35	VPP_IN	POW					1.8 V OTP programming input supply
36	FAST_CLK_REQ	Digital	O	V_IO	PD	PD	Fast clock request from the device
37	NC	NC					Connect to GND
38	NC	NC					Connect to GND
39	PA_LDO_IN	POW					3.3 V supply for PA
40	PA_LDO_IN	POW					3.3 V supply for PA

All digital I/O's (with the exception of SDIO signals) are Hi-Z when the device is in shutdown mode with internal PU/PD according to the "shutdown state" column.
See software release notes for support level.
LOGGER and HOST_IRQ_WL pins are sensed by the device during boot, see CC33xx Hardware Integration.