JAJSG42I May   2009  – September 2018 CC430F5133 , CC430F5135 , CC430F5137 , CC430F6125 , CC430F6126 , CC430F6127 , CC430F6135 , CC430F6137

PRODUCTION DATA.  

  1. 1デバイスの概要
    1. 1.1 特長
    2. 1.2 アプリケーション
    3. 1.3 概要
    4. 1.4 機能ブロック図
  2. 2改訂履歴
  3. 3Device Comparison
    1. 3.1 Related Products
  4. 4Terminal Configuration and Functions
    1. 4.1 Pin Diagrams
    2. 4.2 Signal Descriptions
      1. Table 4-1 CC430F613x and CC430F612x Terminal Functions
      2. Table 4-2 CC430F513x Terminal Functions
  5. 5Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Active Mode Supply Current Into VCC Excluding External Current
    5. 5.5  Typical Characteristics – Active Mode Supply Currents
    6. 5.6  Low-Power Mode Supply Currents (Into VCC) Excluding External Current
    7. 5.7  Typical Characteristics – Low-Power Mode Supply Currents
    8. 5.8  Low-Power Mode With LCD Supply Currents (Into VCC) Excluding External Current
    9. 5.9  Thermal Resistance Characteristics, CC430F51xx
    10. 5.10 Thermal Resistance Characteristics, CC430F61xx
    11. 5.11 Digital Inputs
    12. 5.12 Digital Outputs
    13. 5.13 Typical Characteristics – Outputs, Reduced Drive Strength (PxDS.y = 0)
    14. 5.14 Typical Characteristics – Outputs, Full Drive Strength (PxDS.y = 1)
    15. 5.15 Crystal Oscillator, XT1, Low-Frequency Mode
    16. 5.16 Internal Very-Low-Power Low-Frequency Oscillator (VLO)
    17. 5.17 Internal Reference, Low-Frequency Oscillator (REFO)
    18. 5.18 DCO Frequency
    19. 5.19 PMM, Brownout Reset (BOR)
    20. 5.20 PMM, Core Voltage
    21. 5.21 PMM, SVS High Side
    22. 5.22 PMM, SVM High Side
    23. 5.23 PMM, SVS Low Side
    24. 5.24 PMM, SVM Low Side
    25. 5.25 Wake-up Times From Low-Power Modes and Reset
    26. 5.26 Timer_A
    27. 5.27 USCI (UART Mode) Clock Frequency
    28. 5.28 USCI (UART Mode)
    29. 5.29 USCI (SPI Master Mode) Clock Frequency
    30. 5.30 USCI (SPI Master Mode)
    31. 5.31 USCI (SPI Slave Mode)
    32. 5.32 USCI (I2C Mode)
    33. 5.33 LCD_B Operating Conditions
    34. 5.34 LCD_B Electrical Characteristics
    35. 5.35 12-Bit ADC, Power Supply and Input Range Conditions
    36. 5.36 12-Bit ADC, Timing Parameters
    37. 5.37 12-Bit ADC, Linearity Parameters Using an External Reference Voltage or AVCC as Reference Voltage
    38. 5.38 12-Bit ADC, Linearity Parameters Using the Internal Reference Voltage
    39. 5.39 12-Bit ADC, Temperature Sensor and Built-In VMID
    40. 5.40 REF, External Reference
    41. 5.41 REF, Built-In Reference
    42. 5.42 Comparator_B
    43. 5.43 Flash Memory
    44. 5.44 JTAG and Spy-Bi-Wire Interface
    45. 5.45 RF1A CC1101-Based Radio Parameters
      1. 5.45.1  Recommended Operating Conditions
      2. 5.45.2  RF Crystal Oscillator, XT2
      3. 5.45.3  Current Consumption, Reduced-Power Modes
      4. 5.45.4  Current Consumption, Receive Mode
      5. 5.45.5  Current Consumption, Transmit Mode
      6. 5.45.6  Typical TX Current Consumption, 315 MHz
      7. 5.45.7  Typical TX Current Consumption, 433 MHz
      8. 5.45.8  Typical TX Current Consumption, 868 MHz
      9. 5.45.9  Typical TX Current Consumption, 915 MHz
      10. 5.45.10 RF Receive, Overall
      11. 5.45.11 RF Receive, 315 MHz
      12. 5.45.12 RF Receive, 433 MHz
      13. 5.45.13 RF Receive, 868 or 915 MHz
      14. 5.45.14 Typical Sensitivity, 315 MHz, Sensitivity Optimized Setting
      15. 5.45.15 Typical Sensitivity, 433 MHz, Sensitivity Optimized Setting
      16. 5.45.16 Typical Sensitivity, 868 MHz, Sensitivity Optimized Setting
      17. 5.45.17 Typical Sensitivity, 915 MHz, Sensitivity Optimized Setting
      18. 5.45.18 RF Transmit
      19. 5.45.19 Optimum PATABLE Settings for Various Output Power Levels and Frequency Bands
      20. 5.45.20 Typical Output Power, 315 MHz
      21. 5.45.21 Typical Output Power, 433 MHz
      22. 5.45.22 Typical Output Power, 868 MHz
      23. 5.45.23 Typical Output Power, 915 MHz
      24. 5.45.24 Frequency Synthesizer Characteristics
      25. 5.45.25 Typical RSSI_offset Values
  6. 6Detailed Description
    1. 6.1  Sub-1 GHz Radio
    2. 6.2  CPU
    3. 6.3  Operating Modes
    4. 6.4  Interrupt Vector Addresses
    5. 6.5  Memory Organization
    6. 6.6  Bootloader (BSL)
    7. 6.7  JTAG Operation
      1. 6.7.1 JTAG Standard Interface
      2. 6.7.2 Spy-Bi-Wire Interface
    8. 6.8  Flash Memory
    9. 6.9  RAM
    10. 6.10 Peripherals
      1. 6.10.1  Oscillator and System Clock
      2. 6.10.2  Power-Management Module (PMM)
      3. 6.10.3  Digital I/O
      4. 6.10.4  Port Mapping Controller
      5. 6.10.5  System Module (SYS)
      6. 6.10.6  DMA Controller
      7. 6.10.7  Watchdog Timer (WDT_A)
      8. 6.10.8  CRC16
      9. 6.10.9  Hardware Multiplier
      10. 6.10.10 AES128 Accelerator
      11. 6.10.11 Universal Serial Communication Interface (USCI)
      12. 6.10.12 TA0
      13. 6.10.13 TA1
      14. 6.10.14 Real-Time Clock (RTC_A)
      15. 6.10.15 Voltage Reference (REF)
      16. 6.10.16 LCD_B (Only CC430F613x and CC430F612x)
      17. 6.10.17 Comparator_B
      18. 6.10.18 ADC12_A (Only CC430F613x and CC430F513x)
      19. 6.10.19 Embedded Emulation Module (EEM) (S Version)
      20. 6.10.20 Peripheral File Map
    11. 6.11 Input/Output Diagrams
      1. 6.11.1  Port P1 (P1.0 to P1.4) Input/Output With Schmitt Trigger
      2. 6.11.2  Port P1 (P1.5 to P1.7) Input/Output With Schmitt Trigger
      3. 6.11.3  Port P2 (P2.0 to P2.7) Input/Output With Schmitt Trigger
      4. 6.11.4  Port P3 (P3.0 to P3.7) Input/Output With Schmitt Trigger
      5. 6.11.5  Port P4 (P4.0 to P4.7) Input/Output With Schmitt Trigger (CC430F613x and CC430F612x Only)
      6. 6.11.6  Port P5 (P5.0 and P5.1) Input/Output With Schmitt Trigger
      7. 6.11.7  Port P5 (P5.2 to P5.4) Input/Output With Schmitt Trigger (CC430F613x and CC430F612x Only)
      8. 6.11.8  Port P5 (P5.5 to P5.7) Input/Output With Schmitt Trigger (CC430F613x and CC430F612x Only)
      9. 6.11.9  Port J (PJ.0) JTAG Pin TDO, Input/Output With Schmitt Trigger or Output
      10. 6.11.10 Port J (PJ.1 to PJ.3) JTAG Pins TMS, TCK, TDI/TCLK, Input/Output With Schmitt Trigger or Output
    12. 6.12 Device Descriptor
  7. 7Applications, Implementation, and Layout
    1. 7.1 Application Circuits
  8. 8デバイスおよびドキュメントのサポート
    1. 8.1  使い始めと次の手順
    2. 8.2  Device Nomenclature
    3. 8.3  ツールとソフトウェア
    4. 8.4  ドキュメントのサポート
    5. 8.5  関連リンク
    6. 8.6  Community Resources
    7. 8.7  商標
    8. 8.8  静電気放電に関する注意事項
    9. 8.9  Export Control Notice
    10. 8.10 Glossary
  9. 9メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

6.10.4 Port Mapping Controller

The port mapping controller allows the flexible and reconfigurable mapping of digital functions to port pins of ports P1 through P3 (see Table 6-6). Table 6-7 lists the default settings for all pins that support port mapping.

Table 6-6 Port Mapping, Mnemonics and Functions

VALUE PxMAPy MNEMONIC INPUT PIN FUNCTION
(PxDIR.y = 0)		 OUTPUT PIN FUNCTION
(PxDIR.y = 1)
0 PM_NONE None DVSS
1(1) PM_CBOUT0 – Comparator_B output (on TA0 clock input)
PM_TA0CLK TA0 clock input –
2(1) PM_CBOUT1 – Comparator_B output (on TA1 clock input)
PM_TA1CLK TA1 clock input –
3 PM_ACLK None ACLK output
4 PM_MCLK None MCLK output
5 PM_SMCLK None SMCLK output
6 PM_RTCCLK None RTCCLK output
7(1) PM_ADC12CLK – ADC12CLK output
PM_DMAE0 DMA external trigger input –
8 PM_SVMOUT None SVM output
9 PM_TA0CCR0A TA0 CCR0 capture input CCI0A TA0 CCR0 compare output Out0
10 PM_TA0CCR1A TA0 CCR1 capture input CCI1A TA0 CCR1 compare output Out1
11 PM_TA0CCR2A TA0 CCR2 capture input CCI2A TA0 CCR2 compare output Out2
12 PM_TA0CCR3A TA0 CCR3 capture input CCI3A TA0 CCR3 compare output Out3
13 PM_TA0CCR4A TA0 CCR4 capture input CCI4A TA0 CCR4 compare output Out4
14 PM_TA1CCR0A TA1 CCR0 capture input CCI0A TA1 CCR0 compare output Out0
15 PM_TA1CCR1A TA1 CCR1 capture input CCI1A TA1 CCR1 compare output Out1
16 PM_TA1CCR2A TA1 CCR2 capture input CCI2A TA1 CCR2 compare output Out2
17(2) PM_UCA0RXD USCI_A0 UART RXD (direction controlled by USCI – input)
PM_UCA0SOMI USCI_A0 SPI slave out master in (direction controlled by USCI)
18(2) PM_UCA0TXD USCI_A0 UART TXD (direction controlled by USCI – output)
PM_UCA0SIMO USCI_A0 SPI slave in master out (direction controlled by USCI)
19(3) PM_UCA0CLK USCI_A0 clock input/output (direction controlled by USCI)
PM_UCB0STE USCI_B0 SPI slave transmit enable (direction controlled by USCI – input)
20(4) PM_UCB0SOMI USCI_B0 SPI slave out master in (direction controlled by USCI)
PM_UCB0SCL USCI_B0 I2C clock (open drain and direction controlled by USCI)
21(4) PM_UCB0SIMO USCI_B0 SPI slave in master out (direction controlled by USCI)
PM_UCB0SDA USCI_B0 I2C data (open drain and direction controlled by USCI)
22(5) PM_UCB0CLK USCI_B0 clock input/output (direction controlled by USCI)
PM_UCA0STE USCI_A0 SPI slave transmit enable (direction controlled by USCI – input)
23 PM_RFGDO0 Radio GDO0 (direction controlled by Radio)
24 PM_RFGDO1 Radio GDO1 (direction controlled by Radio)
25 PM_RFGDO2 Radio GDO2 (direction controlled by Radio)
26 Reserved None DVSS
27 Reserved None DVSS
28 Reserved None DVSS
29 Reserved None DVSS
30 Reserved None DVSS
31 (0FFh)(6) PM_ANALOG Disables the output driver and the input Schmitt-trigger to prevent parasitic cross currents when applying analog signals.
(1) Input or output function is selected by the corresponding setting in the port direction register PxDIR.
(2) UART or SPI functionality is determined by the selected USCI mode.
(3) UCA0CLK function takes precedence over UCB0STE function. If the mapped pin is required as UCA0CLK input or output, USCI_B0 is forced to 3-wire SPI mode even if 4-wire mode is selected.
(4) SPI or I2C functionality is determined by the selected USCI mode. In case the I2C functionality is selected the output of the mapped pin drives only the logical 0 to VSS level.
(5) UCB0CLK function takes precedence over UCA0STE function. If the mapped pin is required as UCB0CLK input or output, USCI_A0 is forced to 3-wire SPI mode even if 4-wire mode is selected.
(6) The value of the PM_ANALOG mnemonic is set to 0FFh. The port mapping registers are only 5 bits wide and the upper bits are ignored, resulting in a read value of 31.

Table 6-7 Default Mapping

PIN PxMAPy MNEMONIC INPUT PIN FUNCTION (PxDIR.y = 0) OUTPUT PIN FUNCTION (PxDIR.y = 1)
P1.0/P1MAP0 PM_RFGDO0 None Radio GDO0
P1.1/P1MAP1 PM_RFGDO2 None Radio GDO2
P1.2/P1MAP2 PM_UCB0SOMI/PM_UCB0SCL USCI_B0 SPI slave out master in (direction controlled by USCI),
USCI_B0 I2C clock (open drain and direction controlled by USCI)
P1.3/P1MAP3 PM_UCB0SIMO/PM_UCB0SDA USCI_B0 SPI slave in master out (direction controlled by USCI),
USCI_B0 I2C data (open drain and direction controlled by USCI)
P1.4/P1MAP4 PM_UCB0CLK/PM_UCA0STE USCI_B0 clock input/output (direction controlled by USCI),
USCI_A0 SPI slave transmit enable (direction controlled by USCI – input)
P1.5/P1MAP5 PM_UCA0RXD/PM_UCA0SOMI USCI_A0 UART RXD (direction controlled by USCI – input),
USCI_A0 SPI slave out master in (direction controlled by USCI)
P1.6/P1MAP6 PM_UCA0TXD/PM_UCA0SIMO USCI_A0 UART TXD (direction controlled by USCI – output),
USCI_A0 SPI slave in master out (direction controlled by USCI)
P1.7/P1MAP7 PM_UCA0CLK/PM_UCB0STE USCI_A0 clock input/output (direction controlled by USCI),
USCI_B0 SPI slave transmit enable (direction controlled by USCI – input)
P2.0/P2MAP0 PM_CBOUT1/PM_TA1CLK TA1 clock input Comparator_B output
P2.1/P2MAP1 PM_TA1CCR0A TA1 CCR0 capture input CCI0A TA1 CCR0 compare output Out0
P2.2/P2MAP2 PM_TA1CCR1A TA1 CCR1 capture input CCI1A TA1 CCR1 compare output Out1
P2.3/P2MAP3 PM_TA1CCR2A TA1 CCR2 capture input CCI2A TA1 CCR2 compare output Out2
P2.4/P2MAP4 PM_RTCCLK None RTCCLK output
P2.5/P2MAP5 PM_SVMOUT None SVM output
P2.6/P2MAP6 PM_ACLK None ACLK output
P2.7/P2MAP7 PM_ADC12CLK/PM_DMAE0 DMA external trigger input ADC12CLK output
P3.0/P3MAP0 PM_CBOUT0/PM_TA0CLK TA0 clock input Comparator_B output
P3.1/P3MAP1 PM_TA0CCR0A TA0 CCR0 capture input CCI0A TA0 CCR0 compare output Out0
P3.2/P3MAP2 PM_TA0CCR1A TA0 CCR1 capture input CCI1A TA0 CCR1 compare output Out1
P3.3/P3MAP3 PM_TA0CCR2A TA0 CCR2 capture input CCI2A TA0 CCR2 compare output Out2
P3.4/P3MAP4 PM_TA0CCR3A TA0 CCR3 capture input CCI3A TA0 CCR3 compare output Out3
P3.5/P3MAP5 PM_TA0CCR4A TA0 CCR4 capture input CCI4A TA0 CCR4 compare output Out4
P3.6/P3MAP6 PM_RFGDO1 None Radio GDO1
P3.7/P3MAP7 PM_SMCLK None SMCLK output