JAJSOR2L August   1998  – September 2023 CD4051B , CD4052B , CD4053B

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Revision History
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 AC Performance Characteristics
    7. 6.7 Typical Characteristics
  8. 7 Parameter Measurement Information
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagrams
    3. 8.3 Feature Description
    4. 8.4 Device Functional Modes
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curve
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 ドキュメントの更新通知を受け取る方法
    3. 10.3 サポート・リソース
    4. 10.4 Trademarks
    5. 10.5 静電気放電に関する注意事項
    6. 10.6 用語集
  12. 11Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

6.5 Electrical Characteristics

Over operating free-air temperature range, VSUPPLY = ±5 V, and RL = 100 Ω, (unless otherwise noted)(1)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SIGNAL INPUTS (VIS) AND OUTPUTS (VOS)
VIS (V) VEE (V) VSS (V) VDD (V) TEMP

Quiescent Device Current, IDD Max
 		 0 V 0 V 5 V
 –55°C 60 µA
–40°C 60
25°C 17 60

85°C

 150

125°C

 150
0 V 0 V 10 V
 –55°C 60
–40°C 60
25°C 18 60

85°C

 300

125°C

 300
0 V 0 V 15 V

 		 –55°C 60
–40°C 60
25°C 18 60

85°C

 600

125°C

 600
0 V 0 V 20 V
 –55°C 100
–40°C 100
25°C 18 100

85°C

 3000

125°C

 3000
Drain to Source ON Resistance rON Max
0 ≤ VIS ≤ VDD		 0 V 0 V 5 V –55°C 800 Ω
–40°C 850
25°C 470 1050

85°C

 1200

125°C

 1300
0 V 0 V 10 V –55°C 310
–40°C 300
25°C 180 400

85°C

 520

125°C

 550
0 V 0 15 V –55°C 200
–40°C 210
25°C 125 240

85°C

 300

125°C

 300
Change in ON Resistance
(Between Any Two Channels),
ΔRON		 0 V 0 V 5 V 25°C 15 Ω
0 V 0 V 10 V 10
0 V 0 V 15 V 5
OFF Channel Leakage Current: Any Channel OFF (Max)
or ALL Channels OFF (COMMON OUT/IN) (Max)		 0 V 0 V 18 V
 		 –55°C ± 100 nA
–40°C
25°C ± 0.3 ± 100(2)

85°C

 ± 1000(2)

125°C
ON Channel Leakage Current: Any Channel ON (Max) or
ALL Channels ON (COMMON OUT/IN) (Max)		 5 or 0
 –5 V 0 V 10.5 V
85°C

 ± 800 nA
5
 0 V 0 V 18 V
85°C

 ± 800
Capacitance Input, CIS 0 V 0 V 10 V 25°C 5 pF
Output, COS CD4051 30
Output, COS CD4052 18
Output, COS CD4053 9
Feed through, CIOS 0.2
Prop Delay VDD RL = 200 kΩ 5 V
25°C

 30 60 ns
CL = 50 pF 10 V 15 30
tr, tf = 20 ns 15 V 10 20
CONTROL (ADDRESS OR INHIBIT), VC 
Input Low Voltage, VIL, Max 5 V –55°C 0.8 V
–40°C 0.8
25°C 0.8

85°C

 0.8

125°C

 0.8
10 V –55°C 0.8
–40°C 0.8
25°C 0.8

85°C

 0.8

125°C

 0.8
15 V –55°C 0.8
–40°C 0.8
25°C 0.8

85°C

 0.8

125°C

 0.8
Input High Voltage, VIH, Min 5 V –55°C 3.5 V
–40°C 3.5
25°C 3.5

85°C

 3.5

125°C

 3.5
10 V –55°C 7
–40°C 7
25°C 7

85°C

 7

125°C

 7
15 V –55°C 11
–40°C 11
25°C 11

85°C

 11

125°C

 11
Input current, IIN (Max) VIN = 0, 18 18 V –55°C ±1 µA
–40°C ±1
25°C ±0.6 ±1

85°C

 ±1

125°C

 ±1
Propagation
Delay Time		 Address-to-Signal OUT (Channels ON
or OFF) (See Figure 7-2, Figure 7-3,
and Figure 7-8)		 tr , tf = 20ns,
CL = 50 pF,
RL = 10 kΩ		 0 V 0 V 5 V 450 720 ns
0 V 0 V 10 V 160 320
0 V 0 V 15 V 120 240
–5 V 0 V 5 V 225 450
Propagation
Delay Time		 Inhibit-to-Signal OUT (Channel Turning ON) (See Figure 7-3) tr , tf = 20
ns,
CL = 50 pF,
RL = 1 kΩ		 0 V 0 V 5 V 400 720 ns
0 V 0 V 10 V 160 320
0 V 0 V 15 V 120 240
–10 V 0 V 5 V 200 400
Propagation
Delay Time		 Inhibit-to-Signal OUT (Channel Turning OFF) (See Figure 7-10) tr , tf = 20
ns,
CL = 50 pF,
RL = 10 kΩ		 0 V 0 V 5 V 200 450 ns
0 V 0 V 10 V 90 210
0 V 0 V 15 V 70 160
–10 V 0 V 5 V 130 300
Input Capacitance, CIN (Any Address or Inhibit Input) –5 V 0 V 5 V 25°C 5 7.5 pF
(1) Peak-to-Peak voltage symmetrical about (VDD – VEE) / 2.
(2) Determined by minimum feasible leakage measurement for automatic testing.