JAJSOR2M August   1998  – November 2024 CD4051B , CD4052B , CD4053B

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 AC Performance Characteristics
    7. 5.7 Typical Characteristics
  7. 6 Parameter Measurement Information
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagrams
    3. 7.3 Feature Description
    4. 7.4 Device Functional Modes
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curve
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 ドキュメントの更新通知を受け取る方法
    3. 9.3 サポート・リソース
    4. 9.4 Trademarks
    5. 9.5 静電気放電に関する注意事項
    6. 9.6 用語集
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

6 Parameter Measurement Information

CD4051B CD4052B CD4053B Typical Bias Voltages Figure 6-1 Typical Bias Voltages
Note:

The ADDRESS (digital-control inputs) and INHIBIT logic levels are: 0 = VSS
and 1 = VDD. The analog signal (through the TG) may swing from VEE to VDD.

CD4051B CD4052B CD4053B Waveforms, Channel Being Turned ON (RL = 1 kΩ)Figure 6-2 Waveforms, Channel Being Turned ON (RL = 1 kΩ)
CD4051B CD4052B CD4053B Waveforms, Channel Being Turned OFF (RL = 1 kΩ)Figure 6-3 Waveforms, Channel Being Turned OFF (RL = 1 kΩ)
CD4051B CD4052B CD4053B OFF Channel Leakage Current – Any Channel OFF Figure 6-4 OFF Channel Leakage Current – Any Channel OFF
CD4051B CD4052B CD4053B On Channel Leakage Current – Any Channel On Figure 6-5 On Channel Leakage Current – Any Channel On
CD4051B CD4052B CD4053B OFF Channel Leakage Current – All Channels OFF Figure 6-6 OFF Channel Leakage Current – All Channels OFF
CD4051B CD4052B CD4053B Propagation Delay – Address Input to Signal Output Figure 6-7 Propagation Delay – Address Input to Signal Output
CD4051B CD4052B CD4053B Propagation Delay – Inhibit Input to Signal Output Figure 6-8 Propagation Delay – Inhibit Input to Signal Output
CD4051B CD4052B CD4053B Input Voltage Test Circuits (Noise Immunity) Figure 6-9 Input Voltage Test Circuits (Noise Immunity)
CD4051B CD4052B CD4053B Quiescent Device CurrentFigure 6-10 Quiescent Device Current
CD4051B CD4052B CD4053B Channel ON Resistance Measurement CircuitFigure 6-11 Channel ON Resistance Measurement Circuit
CD4051B CD4052B CD4053B Input Current Figure 6-12 Input Current
CD4051B CD4052B CD4053B Feed-Through (All Types)Figure 6-13 Feed-Through (All Types)
CD4051B CD4052B CD4053B Crosstalk Between Any Two Channels (All Types)Figure 6-14 Crosstalk Between Any Two Channels (All Types)
CD4051B CD4052B CD4053B Crosstalk Between Duals or Triplets (CD4052B, CD4053B) Figure 6-15 Crosstalk Between Duals or Triplets (CD4052B, CD4053B)
CD4051B CD4052B CD4053B Typical Time-Division Application of the CD4052B
Special Considerations: In applications where separate power sources are used to drive VDD and the signal inputs, the VDD current capability should exceed VDD/RL (RL = effective external load). This provision avoids permanent current flow or clamp action on the VDD supply when power is applied or removed from the CD4051B, CD4052B or CD4053B.
Figure 6-16 Typical Time-Division Application of the CD4052B
CD4051B CD4052B CD4053B 24-to-1 MUX Addressing Figure 6-17 24-to-1 MUX Addressing