JAJSVA8B November   1998  – August 2024 CD54AC257 , CD54ACT257 , CD74AC257 , CD74ACT257 , CD74ACT258

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 概要
  4. 3 Pin Configuration and Functions
  5. 4 Specifications
    1. 4.1 Absolute Maximum Ratings
    2. 4.2 Recommended Operating Conditions
    3. 4.3 Thermal Information
    4. 4.4 Electrical Characteristics
    5. 4.5 Switching Specifications
  6. 5 Parameter Measurement Information
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Device Functional Modes
  8. 7 Application and Implementation
    1. 7.1 Power Supply Recommendations
    2. 7.2 Layout
      1. 7.2.1 Layout Guidelines
  9. 8 Device and Documentation Support
    1. 8.1 Documentation Support (Analog)
      1. 8.1.1 Related Documentation
    2. 8.2 ドキュメントの更新通知を受け取る方法
    3. 8.3 サポート・リソース
    4. 8.4 Trademarks
    5. 8.5 静電気放電に関する注意事項
    6. 8.6 用語集
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

デバイスごとのパッケージ図は、PDF版データシートをご参照ください。

メカニカル・データ（パッケージ｜ピン）
  • D|16
サーマルパッド・メカニカル・データ

3 Pin Configuration and Functions

CD54AC257 CD74AC257 CD54ACT257 CD74ACT257 CD74ACT258 CD54AC257, CD54ACT257 J Package; CD74AC257, CD74ACT257, CD74ACT258 N or D Package; 16-Pin CDIP, PDIP or SOIC (Top View)Figure 3-1 CD54AC257, CD54ACT257 J Package; CD74AC257, CD74ACT257, CD74ACT258 N or D Package; 16-Pin CDIP, PDIP or SOIC (Top View)
Table 3-1 Pin Functions
PIN TYPE(1) DESCRIPTION
NAME NO.
S 1 I Select
1I0 2 I Channel 1 Input 0
1I1 3 I Channel 1 Input 1
1Y 4 O Channel 1 Output
2I0 5 I Channel 2 Input 0
2I1 6 I Channel 2 Input 1
2Y 7 O Channel 2 Output
GND 8 G Ground
3Y 9 O Channel 3 Output
3I1 10 I Channel 3 Input 1
3I0 11 I Channel 3 Input 0
4Y 12 O Channel 4 Output
4I1 13 I Channel 4 Input 1
4I0 14 I Channel 4 Input 0
OE 15 I Output Enable
VCC 16 P Positive Supply
(1) I = Input, O = Output, I/O = Input or Output, G = Ground, P = Power.