JAJSG05H November   2009  – October 2024 CDC3RL02

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Device Comparison
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Low Additive Noise
      2. 7.3.2 Regulated 1.8V Externally Available I/O Supply
      3. 7.3.3 Ultra-Small 8-bump YFP 0.4mm Pitch WCSP Package
    4. 7.4 Device Functional Modes
  9. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Input Clock Squarer
      2. 8.1.2 Output Stage
      3. 8.1.3 LDO
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curve
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 ドキュメントの更新通知を受け取る方法
    3. 9.3 サポート・リソース
    4. 9.4 Trademarks
    5. 9.5 静電気放電に関する注意事項
    6. 9.6 用語集
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

6.5 Electrical Characteristics

over operating free-air temperature range (unless otherwise noted)
PARAMETERTEST CONDITIONSMINTYPMAXUNIT
LDO
VOUTLDO output voltageIOUT = 50mA1.711.81.89V
CLDOExternal load capacitance110μF
IOUT(SC)Short circuit output currentRL = 0Ω100mA
IOUT(PK)Peak output currentVBATT = 2.3V, VLDO = VOUT – 5%100mA
PSRPower supply rejectionVBATT = 2.3V, IOUT = 2mA,fIN= 217Hz and 1kHz60dB
fIN= 3.25MHz40
tsuLDO startup timeVBATT = 2.3V, CLDO = 1μF,
CLK_REQ_n to VIH = 1.71V		0.2ms
VBATT = 5.5V, CLDO = 10μF,
CLK_REQ_n to VIH = 1.71V		1
POWER CONSUMPTION
ISBStandby currentDevice in standby (all VCLK_REQ_n = 0V)0.21μA
ICCSStatic current consumptionDevice active but not switching0.41mA
IOBOutput buffer average currentfIN = 26MHz, CLOAD = 50pF4.2mA
CPDOutput power dissipation capacitancefIN = 26MHz44pF
MCLK_IN INPUT
IIMCLK_IN, CLK_REQ_1/2 leakage currentVI = VIH or GND1μA
CIMCLK_IN capacitancefIN = 26MHz4.75pF
RIMCLK_IN impedancefIN = 26MHz6kΩ
fINMCLK_IN frequency range1026100MHz
MCLK_IN LVCMOS SOURCE
Additive phase noisefIN = 26MHz, tr/tf ≤ 1ns1kHz offset–140dBc/Hz
10kHz offset–149
100kHz offset–153
1MHz offset–148
Additive jitterfIN = 26MHz, VPP = 0.8V, BW = 10MHz to 5MHz0.37ps (rms)
tDLMCLK_IN to CLK_OUT_n propagation delay11ns
DCLOutput duty cyclefIN = 26MHz, DCIN = 50%45%50%55%
MCLK_IN SINUSOIDAL SOURCE
VMAInput amplitude0.31.8V
Additive phase noisefIN = 26MHz, VMA = 1.8VPP1kHz offset–141dBc/Hz
10kHz offset–149
100kHz offset–152
1MHz offset–148
fIN = 26MHz, VMA = 0.8VPP1kHz offset–139
10kHz offset–146
100kHz offset–150
1MHz offset–146
Additive jitterfIN = 26MHz, VMA = 1.8VPP, BW = 10MHz to 5MHz0.41ps (RMS)
tDSMCLK_IN to CLK_OUT_1/2 propagation delay12ns
DCsOutput duty cyclefIN = 26MHz, VMA > 1.8VPP45%50%55%
CLK_OUT_N OUTPUTS
tr20% to 80% rise timeCL = 10pF to 50pF15.2ns
tf20% to 80% fall timeCL = 10pF to 50pF15.2ns
tskChannel-to-channel skewCL = 10pF to 50pF (CL1 = CL2)–0.50.5ns
VOHHigh-level output voltageIOH = –100μA, reference to VLDO–0.1V
IOH = –8mA1.2
VOLLow-level output voltageIOL = 20μA0.2V
IOL = 8mA0.55