JAJSTU7 データシート

JAJSTU7H August 2007 – July 2024 CDCE937 , CDCEL937

PRODUCTION DATA

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）

PW|20
- MPDS362A

サーマルパッド・メカニカル・データ

発注情報

5.5 Electrical Characteristics

over recommended operating free-air temperature range (unless otherwise noted)

PARAMETER		TEST CONDITIONS		MIN	TYP⁽¹⁾	MAX	UNIT
I_DD	Supply current (see Figure 5-1)	All outputs off, f_(CLK) = 27 MHz, f_(VCO) = 135 MHz	All PLLS on		29		mA
I_DD	Supply current (see Figure 5-1)	All outputs off, f_(CLK) = 27 MHz, f_(VCO) = 135 MHz	Per PLL		9		mA
I_DDOUT	Output supply current (see Figure 5-2 and Figure 5-3)	No load, all outputs on, f_OUT = 27 MHz	CDCE937, V_DDOUT = 3.3 V		3.1		mA
I_DDOUT	Output supply current (see Figure 5-2 and Figure 5-3)	No load, all outputs on, f_OUT = 27 MHz	CDCEL937, V_DDOUT = 1.8 V		1.5		mA
I_DD(PD)	Power-down current	Every circuit powered down except SDA/SCL, f_IN = 0 MHz, V_DD = 1.9 V			50		µA
V_(PUC)	Supply voltage Vdd threshold for power-up control circuit			0.85		1.45	V
f_(VCO)	VCO frequency range of PLL			80		230	MHz
f_OUT	LVCMOS output frequency	Vddout = 3.3 V		230			MHz
f_OUT	LVCMOS output frequency	Vddout = 1.8 V		230			MHz
LVCMOS PARAMETER
V_IK	LVCMOS input voltage	V_DD = 1.7 V, I_I = –18 mA				–1.2	V
I_I	LVCMOS Input current	VI = 0 V or V_DD, V_DD = 1.9 V				±5	µA
I_IH	LVCMOS Input current for S0/S1/S2	V_I = V_DD, V_DD = 1.9 V				5	µA
I_IL	LVCMOS Input current for S0/S1/S2	V_I = 0 V, V_DD = 1.9 V				–4	µA
C_I	Input capacitance at Xin/Clk	V_I(Clk) = 0 V or V_DD			6		pF
	Input capacitance at Xout	V_I(Xout) = 0 V or V_DD			2
	Input capacitance at S0/S1/S2	V_IS = 0 V or V_DD			3
CDCE937 – LVCMOS FOR Vddout = 3.3 V
V_OH	LVCMOS high-level output voltage	Vddout = 3 V, I_OH = –0.1 mA		2.9			V
		Vddout = 3 V, I_OH = –8 mA		2.4
		Vddout = 3 V, I_OH = –12 mA		2.2
V_OL	LVCMOS low-level output voltage	Vddout = 3 V, I_OL = 0.1 mA				0.1	V
		Vddout = 3 V, I_OL = 8 mA				0.5
		Vddout = 3 V, I_OL = 12 mA				0.8
t_PLH, t_PHL	Propagation delay	All PLL bypass			3.2		ns
t_r/t_f	Rise and fall time	Vddout = 3.3 V (20%–80%)			0.6		ns
t_jit(cc)	Cycle-to-cycle jitter⁽²⁾⁽³⁾	1 PLL switching, Y2-to-Y3			60	90	ps
t_jit(cc)	Cycle-to-cycle jitter⁽²⁾⁽³⁾	3 PLL switching, Y2-to-Y7			100	150	ps
t_jit(per)	Peak-to-peak period jitter⁽³⁾	1 PLL switching, Y2-to-Y3			70	100	ps
t_jit(per)	Peak-to-peak period jitter⁽³⁾	3 PLL switching, Y2-to-Y7			120	180	ps
t_sk(o)	Output skew⁽⁴⁾ (see Table 7-2)	f_OUT = 50 MHz, Y1-to-Y3				60	ps
t_sk(o)	Output skew⁽⁴⁾ (see Table 7-2)	f_OUT = 50 MHz, Y2-to-Y5				160	ps
odc	Output duty cycle⁽⁵⁾	f_VCO = 100 MHz, Pdiv = 1		45%		55%
CDCE937 – LVCMOS FOR Vddout = 2.5 V
V_OH	LVCMOS high-level output voltage	Vddout = 2.3 V, I_OH = –0.1 mA		2.2			V
		Vddout = 2.3 V, I_OH = –6 mA		1.7
		Vddout = 2.3 V, I_OH = –10 mA		1.6
V_OL	LVCMOS low-level output voltage	Vddout = 2.3 V, I_OL = 0.1 mA				0.1	V
		Vddout = 2.3 V, I_OL = 6 mA				0.5
		Vddout = 2.3 V, I_OL = 10 mA				0.7
t_PLH, t_PHL	Propagation delay	All PLL bypass			3.4		ns
t_r/t_f	Rise and fall time	Vddout = 2.5 V (20%–80%)			0.8		ns
t_jit(cc)	Cycle-to-cycle jitter⁽²⁾⁽³⁾	1 PLL switching, Y2-to-Y3			60	90	ps
t_jit(cc)	Cycle-to-cycle jitter⁽²⁾⁽³⁾	3 PLL switching, Y2-to-Y7			100	150	ps
t_jit(per)	Peak-to-peak period jitter⁽⁴⁾	1 PLL switching, Y2-to-Y3			70	100	ps
t_jit(per)	Peak-to-peak period jitter⁽⁴⁾	3 PLL switching, Y2-to-Y7			120	180	ps
t_sk(o)	Output skew⁽⁴⁾ (see Table 7-2)	f_OUT = 50 MHz, Y1-to-Y3				60	ps
t_sk(o)	Output skew⁽⁴⁾ (see Table 7-2)	f_OUT = 50 MHz, Y2-to-Y5				160	ps
odc	Output duty cycle⁽⁵⁾	f_(VCO) = 100 MHz, Pdiv = 1		45%		55%
CDCEL937 – LVCMOS FOR Vddout = 1.8 V
V_OH	LVCMOS high-level output voltage	Vddout = 1.7 V, I_OH = –0.1 mA		1.6			V
		Vddout = 1.7 V, I_OH = –4 mA		1.4
		Vddout = 1.7 V, I_OH = –8 mA		1.1
V_OL	LVCMOS low-level output voltage	Vddout = 1.7 V, I_OL = 0.1 mA				0.1	V
		Vddout = 1.7 V, I_OL = 4 mA				0.3
		Vddout = 1.7 V, I_OL = 8 mA				0.6
t_PLH, t_PHL	Propagation delay	All PLL bypass			2.6		ns
t_r/t_f	Rise and fall time	Vddout= 1.8 V (20%–80%)			0.7		ns
t_jit(cc)	Cycle-to-cycle jitter⁽²⁾⁽³⁾	1 PLL switching, Y2-to-Y3			70	120	ps
t_jit(cc)	Cycle-to-cycle jitter⁽²⁾⁽³⁾	3 PLL switching, Y2-to-Y7			100	150	ps
t_jit(per)	Peak-to-peak period jitter⁽³⁾	1 PLL switching, Y2-to-Y3			90	140	ps
t_jit(per)	Peak-to-peak period jitter⁽³⁾	3 PLL switching, Y2-to-Y7			120	190	ps
t_sk(o)	Output skew⁽⁴⁾ (see Table 7-2)	f_OUT = 50 MHz, Y1-to-Y3				60	ps
t_sk(o)	Output skew⁽⁴⁾ (see Table 7-2)	f_OUT = 50 MHz, Y2-to-Y5				160	ps
odc	Output duty cycle⁽⁵⁾	f_(VCO) = 100 MHz, Pdiv = 1		45%		55%
SDA AND SCL
V_IK	SCL and SDA input clamp voltage	V_DD = 1.7 V; I_I = –18 mA				–1.2	V
I_IH	SCL and SDA input current	V_I = V_DD; V_DD = 1.9 V				±10	µA
V_IH	SDA/SCL input high voltage⁽⁶⁾			0.7 × V_DD			V
V_IL	SDA/SCL input low voltage⁽⁶⁾					0.3 × V_DD	V
V_OL	SDA low-level output voltage	I_OL = 3 mA, V_DD = 1.7 V				0.2 × V_DD	V
C_I	SCL/SDA Input capacitance	V_I = 0 V or V_DD			3	10	pF

(1) All typical values are at respective nominal V_DD.

(2) 10000 cycles.

(3) Jitter depends on configuration. Data is taken under the following conditions: 1-PLL is f_IN = 27 MHz and Y2/3 = 27 MHz (measured at Y2); 3-PLL is f_IN = 27 MHz, Y2/3 = 27 MHz (measured at Y2), Y4/5 = 16.384 MHz, and Y6/7 = 74.25 MHz.

(4) The tsk(o) specification is only valid for equal loading of each bank of outputs, and outputs are generated from the same divider; data taking on rising edge (tr).

(5) odc depends on output rise and fall time (t_r/t_f).

(6) SDA and SCL pins are 3.3-V tolerant.