SCAS881C August   2009  – January 2016 CDCLVP2102

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics: LVCMOS Input, at VCC = 2.375 V to 3.6 V
    6. 6.6  Electrical Characteristics: Differential Input, at VCC = 2.375 V to 3.6 V
    7. 6.7  Electrical Characteristics: LVPECL Output, at VCC = 2.375 V to 2.625 V
    8. 6.8  Electrical Characteristics: LVPECL Output, at VCC = 3 V to 3.6 V
    9. 6.9  Timing Requirements, at VCC = 2.375 V to 2.625 V
    10. 6.10 Timing Requirements, at VCC = 3 V to 3.6 V
    11. 6.11 Typical Characteristics
  7. 7 Parameter Measurement Information
    1. 7.1 Test Configurations
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
    4. 8.4 Device Functional Modes
      1. 8.4.1 LVPECL Output Termination
      2. 8.4.2 Input Termination
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
    3. 11.3 Thermal Considerations
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Community Resources
    3. 12.3 Trademarks
    4. 12.4 Electrostatic Discharge Caution
    5. 12.5 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

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発注情報

9 Application and Implementation

NOTE

Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.

9.1 Application Information

The CDCLVP2102 is a low additive jitter LVPECL fan-out buffer that can generate two copies each of two independent LVPECL, LVDS, or LVCMOS inputs. The CDCLVP2102 can accept reference clock frequencies up to 2 GHz while providing low output skew.

9.2 Typical Application

Figure 20 shows a fan-out buffer for line-card application.

CDCLVP2102 block_diagram_scas881.gif Figure 20. CDCLVP2102 Typical Application

9.2.1 Design Requirements

The CDCLVP2102 shown in Figure 20 is configured to be able to select two inputs: a 156.25-MHz LVPECL clock from the backplane, or a secondary 156.25-MHz LVCMOS 2.5-V oscillator. Either signal can be then fanned out to desired devices, as shown.

The configuration example is driving 4 LVPECL receivers in a line-card application with the following properties:

  • The PHY device has internal AC coupling and appropriate termination and biasing. The CDCLVP2102 must be provided with 86-Ω emitter resistors near the driver for proper operation.
  • The ASIC is capable of DC coupling with a 2.5-V LVPECL driver such as the CDCLVP2102. This ASIC features internal termination so no additional components are needed.
  • The FPGA requires external AC coupling but has internal termination. Again, 86-Ω emitter resistors are placed near the CDCLVP2102, and 0.1 μF are placed to provide AC coupling. Similarly, the CPU is internally terminated and requires external AC coupling capacitors.

9.2.2 Detailed Design Procedure

Refer to Input Termination for proper input terminations, dependent on single ended or differential inputs.

Refer to LVPECL Output Termination for output termination schemes depending on the receiver application.

Unused outputs can be left floating.

In Figure 20, the PHY, ASIC, and FPGA/CPU require different schemes. Power supply filtering and bypassing is critical for low-noise applications.

See Power Supply Recommendations for recommended filtering techniques. A reference layout is provided on the CDCLVP2102 Evaluation Module, Low Additive Phase Noise Clock Buffer Evaluation Board User's Guide (SCAU033).

9.2.3 Application Curves

CDCLVP2102 ref_noise_1204.png
Reference signal is low-noise Crystek XO CPRO33.156.25
32 fs, RMS 10 kHz to 20 MHz
Figure 21. CDCLVP21xx Reference Phase Noise
CDCLVP2102 output_noise_1204.png
57 fs, RMS 10 kHz to 20 MHz
Figure 22. CDCLVP21xx Output Phase Noise

The low additive noise of the CDCLVP2102 can be shown in this line-card application. The low noise 156.25 MHz XO with 32-fs, RMS jitter drives the CDCLVP2102, resulting in 57 fs, RMS when integrated from 10 kHz to 20 MHz. The resultant additive jitter is a low 47 fs, RMS for this configuration.