SCAS759C April   2004  – July 2017 CDCM1802

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics
    6. 6.6  Switching Characteristics
    7. 6.7  Jitter Characteristics
    8. 6.8  Supply Current Electrical Characteristics
    9. 6.9  Control Input Characteristics
    10. 6.10 Timing Requirements
    11. 6.11 Bias Voltage VBB
    12. 6.12 Typical Characteristics
  7. 7 Parameter Measurement Information
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
    4. 8.4 Device Functional Modes
      1. 8.4.1 Control Pin Settings
      2. 8.4.2 Device Behavior During RESET and Control Pin Switching
        1. 8.4.2.1 Output Behavior When Enabling the Device (EN = 0 → 1)
        2. 8.4.2.2 Enabling a Single Output Stage
  9. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 LVPECL Receiver Input Termination
      2. 9.1.2 LVCMOS Receiver Input Termination
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curve
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
    3. 11.3 Thermal Considerations
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Third-Party Products Disclaimer
    2. 12.2 Documentation Support
      1. 12.2.1 Related Documentation
    3. 12.3 Community Resources
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

1 Features

  • Distributes One Differential Clock Input to One LVPECL Differential Clock Output and One LVCMOS Single-Ended Output
  • Programmable Output Divider for Both LVPECL and LVCMOS Outputs
  • 1.6-ns Output Skew Between LVCMOS and LVPECL Transitions Minimizing Noise
  • 3.3-V Power Supply (2.5-V Functional)
  • Signaling Rate Up to 800-MHz LVPECL and
    200-MHz LVCMOS
  • Differential Input Stage for Wide Common-Mode Range Also Provides VBB Bias Voltage Output for Single-Ended Input Signals
  • Receiver Input Threshold ±75 mV
  • 16-Pin VQFN Package (3.00 mm × 3.00 mm)

2 Applications

  • Networking and Data Communications
  • Medical Imaging
  • Portable Test and Measurement
  • High-end A/V

3 Description

The CDCM1802 clock driver distributes one pair of differential clock input to one LVPECL differential clock output pair, Y0 and Y0, and one single-ended LVCMOS output, Y1. It is specifically designed for driving 50-Ω transmission lines. The LVCMOS output is delayed by 1.6 ns over the PECL output stage to minimize noise impact during signal transitions.

The CDCM1802 has two control pins, S0 and S1, to select different output mode settings. The S[1:0] pins are 3-level inputs. Additionally, an enable pin EN is provided to disable or enable all outputs simultaneously. The CDCM1802 is characterized for operation from −40°C to 85°C.

For single-ended driver applications, the CDCM1802 provides a VBB output pin that can be directly connected to the unused input as a common-mode voltage reference.

Device Information(1)

PART NUMBER PACKAGE BODY SIZE (NOM)
CDCM1802 VQFN (16) 3.00 mm × 3.00 mm
  1. For all available packages, see the orderable addendum at the end of the data sheet.

Application Example

CDCM1802 APPLICATION.gif