The CDCM9102 is a low-jitter clock generator designed to provide reference clocks for communications standards such as PCI Express™. The device supports up to PCIE gen3 and is easy to configure and use. The CDCM9102 provides two 100-MHz differential clock ports. The output types supported for these ports include LVPECL, LVDS, or a pair of LVCMOS buffers. HCSL signaling is supported using an AC-coupled network. The user configures the output buffer type desired by strapping device pins. Additionally, a single-ended 25-MHz clock output port is provided. Uses for this port include general-purpose clocking, clocking Ethernet PHYs, or providing a reference clock for additional clock generators. All clocks generated are derived from a single external 25-MHz crystal.
PART NUMBER | PACKAGE | BODY SIZE (NOM) |
---|---|---|
CDCM9102 | VQFN (32) | 5.00 mm × 5.00 mm |
Changes from * Revision (February 2012) to A Revision
PACKAGED DEVICES | FEATURES | TA |
---|---|---|
CDCM9102RHBT | 32-pin VQFN (RHB) package, small tape and reel | –40°C to 85°C |
CDCM9102RHBR | 32-pin VQFN (RHB) package, tape and reel |
PIN | TYPE(1) | DESCRIPTION | |
---|---|---|---|
NAME | NO. | ||
POWER SUPPLIES | |||
GND | Thermal pad, 14, 22 | G | Power supply ground and thermal relief |
REGCAP1 | 19 | P | Capacitor for internal regulator, connect 10-μF Y5V capacitor to GND |
REGCAP2 | 17 | P | Capacitor for internal regulator, connect 10-μF Y5V capacitor to GND |
VDD1 | 4 | P | Power Supply, OUT0 clock port |
VDD2 | 1 | P | Power Supply, OUT1 clock port |
VDD3 | 9 | P | Power supply, low-noise clock generator |
VDD4 | 16 | P | Power supply, low-noise clock generator |
VDD5 | 18 | P | Power supply, low-noise clock generator |
VDD6 | 20 | P | Power supply, crystal oscillator input |
DEVICE CONFIGURATION AND CONTROL | |||
NC | 8, 13, 15, 24–32 | — | No connection permitted |
OE | 7 | O | Output enable/shutdown control input (see Table 2) |
OS1 | 10 | O | Output format select control inputs (see Table 3) |
OS0 | 11 | O | Output format select control inputs (see Table 3) |
RESET | 12 | I | Device reset input (active-low) (see Table 4)(2) |
CRYSTAL OSCILLATOR | |||
XIN | 21 | I | Parallel resonant crystal input (25 MHz) |
DEVICE OUTPUTS | |||
OSCOUT | 23 | O | Oscillator output port (25 MHz) |
OUT0N | 5 | O | Output 0 – negative terminal (100 MHz) |
OUT0P | 6 | O | Output 0 – positive terminal (100 MHz) |
OUT1N | 2 | O | Output 1 – negative terminal (100 MHz) |
OUT1P | 3 | O | Output 1 – positive terminal (100 MHz) |