JAJSH89D May 2012 – April 2019 CDCUN1208LP
PRODUCTION DATA.
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
fOUT | Output frequency | 0.008 | 400 | MHz | ||
VCM | Output common mode voltage,
VDDOx = 2.5/3.3 V |
RL = 100 Ω | 1.125 | 1.2 | 1.275 | V |
Output common mode voltage,
VDDOx = 1.8 V |
RL = 100 Ω | 0.9 | V | |||
|VOD| | Differential output voltage | RL = 100 Ω, single-ended Pk-Pk | 250 | 400 | 550 | mV |
ΔVOD | Change in magnitude of VOD for complementary output states | RL = 100 Ω | –50 | 50 | mV | |
Vring | Output overshoot and undershoot | Percentage of output amplitude VOD | 20% | |||
VOS | Output AC common mode | VIN, DIFF, PP = 0.9 V, RL = 100 Ω, 2 pF | 150 | mVP-P | ||
TADDJIT | Additive jitter(1) | fout = 100 MHz, 10k-20M integration bandwidth,
RL = 100 Ω |
200 | fs, rms | ||
fout = 400 MHz, 10k-20M integration bandwidth,
RL = 100 Ω |
180 | |||||
tR/tF | Output rise/fall time | ERC = Slow, 20% to 80%, ZL = 100 Ω, 1pF,
VDDOx = 3.3 V |
800 | ps | ||
ERC = Slow, 20% to 80%, ZL = 100 Ω, 1pF,
VDDOx = 1.8 V |
700 | |||||
ERC = Medium., 20% to 80%, ZL = 100 Ω, 1pF,
VDDOx = 3.3 V |
600 | |||||
ERC = Medium., 20% to 80%, ZL = 100 Ω, 1pF,
VDDOx = 1.8 V |
500 | |||||
ERC = Fast, 20% to 80%, Z L = 100 Ω, 1 pF | 300 | |||||
ODC | Output duty cycle | 50/50 Input duty cycle | 45% | 55% | ||
ISP
ISN |
Output short circuit current (single ended) | Shorted to GND | –24 | 24 | mA | |
|IPN| | Output short circuit current (differential) | Complementary outputs shorted together | 12 | mA | ||
TDLYO | Propagation delay | ERC set to high rate. Input tr, tf > 0.6 V/ns, RL = 100 Ω, VDD = 2.5 V, 3.3 V | 3.3 | ns | ||
ERC set to high rate. Input tr, tf > 0.6 V/ns, RL = 100 Ω, VDD = 1.8 V | 3.8 | |||||
tSKEW | Skew between outputs | ERC set to high rate. Input tr, tf > 0.6 V/ns, Equal VDDOx,
RL = 100 Ω |
35 | 50 | ps | |
tOE | Output enable to stable clock output | Pin mode. fout = 100 MHz, device in active mode with outputs disabled, OE asserted | 20 | µs | ||
tPD | PD de-asserted to stable clock output | Host mode, fout = 100 MHz, device in power down mode, PD de-asserted | 20 | µs | ||
tPU | Time from power applied to stable clock output(2) | Pin mode, fout = 100 MHz, OE asserted, measured from time VDD is valid to stable output. | 1 | ms |