JAJSH89D May 2012 – April 2019 CDCUN1208LP
PRODUCTION DATA.
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
fOUT | Output frequency | 0.008 | 400 | MHz | ||
Vmax | Absolute maximum output voltage(1) | See Figure 1 | 1.15 | V | ||
Vmin | Absolute minimum output voltage(2) | See Figure 1 | –0.3 | V | ||
VOH | Single-ended output voltage – high(3) | RL = single ended to GND = 50 Ω, CL = 2 pF,
VDDOx = 2.5 V, 3.3 V See Figure 18 |
600 | mV | ||
RL = single ended to GND = 50 Ω, CL = 2 pF,
VDDOx = 1.8 V See Figure 18 |
550 | |||||
VOL | Single-ended output voltage – low(3) | RL = single ended to GND = 50 Ω, CL = 2 pF,
See Figure 18 |
150 | mV | ||
VCROSS | Output crossing point voltage(3) | See Figure 1 | 250 | 550 | mV | |
VCROSSΔ | VCROSS Total variation(3) | See Figure 2 | 140 | mV | ||
VRB | Ring back voltage margin(3) | See Figure 3 | –100 | 100 | mV | |
TSTABLE | Time before VRB is Allowed(3),(4) | See Figure 3 | 500 | ps | ||
VOS | Output AC common mode | VIN, DIFF, PP = 0.9 V, RL = single ended to GND = 50 Ω, 2 pF | 75 | 125 | mVP-P | |
TjitHCSL | Additive jitter, input set to HCSL(5) | fOUT = 100 MHz, 10k-20M integration bandwidth. Differential measurement | 380 | fs, rms | ||
TjitLVDS | Additive jitter, input set to LVDS(5) | fOUT = 100 MHz, 10k-20M integration bandwidth. Differential measurement | 280 | fs, rms | ||
tR/tF | Output rise/fall time(6) | Slow, +150-mV differential, see Figure 4, VDDOx = 3.3 V | 300 | ps | ||
Slow, +150-mV differential, see Figure 4, VDDOx = 1.8 V | 230 | |||||
Med., +150-mV differential, see Figure 4, VDDOx = 3.3 V | 240 | |||||
Med., +150-mV differential, see Figure 4, VDDOx = 1.8 V | 180 | |||||
Fast, +150-mV differential, see Figure 4 | 140 | |||||
TMRF | Output rise/fall time matching | See Figure 5 | 20% | |||
ODC | Output duty cycle(7) | Differential measurement, see Figure 6 | 45% | 55% | ||
TDLYO | Propagation delay | ERC set to high rate. Input tr, tf > 0.6 V/ns, VDD = 2.5 V, 3.3 V | 3.8 | ns | ||
ERC set to high rate. Input tr, tf > 0.6 V/ns, VDD = 1.8 V | 4.3 | |||||
tSKEW | Skew between outputs(8) | Differential Measurement, Input tr, tf > 0.6 V/ns | 35 | 50 | ps | |
tOE | Output enable to stable clock output | Pin mode, fout = 100 MHz, device in active mode with outputs disabled, OE asserted | 2 | µs | ||
tPD | PD de-asserted to stable clock output | Host mode, fout = 100 MHz, device in power down mode, PD de-asserted | 15 | µs | ||
tPU | Time from power applied to stable clock output(9) | Pin mode, fout = 100 MHz, OE asserted, measured from time VDD is valid to stable output | 1 | ms |