JAJSH89D May 2012 – April 2019 CDCUN1208LP
PRODUCTION DATA.
In host configuration mode, the OE pin is no longer available; thus buffers are controlled individually through the host interface. The input multiplexer can be controlled either through the pin or through the device registers, in accordance with Table 12.
When the host interface is enabled, certain pins take on alternative functions, according to Table 8.
The CDCUN1208LP samples the MODE pin after the device exits the power-on reset (POR) state. The device is placed in the RESET state in one of two ways: a POR circuit automatically resets the device after power is applied; or through the RESET bit (R15[1]) in register memory (see Table 12). This RESET bit is only accessible in host configuration mode. If the MODE pin (pin 11) is open (no connection), then the device is placed in the pin configuration mode and all settings are determined by the state of various pins according to Table 1 and Figure 28. If the MODE pin is low, then device enables the SPI interface; and, if MODE is high, then I2C is enabled.