JAJSH89D
May 2012 – April 2019
CDCUN1208LP
PRODUCTION DATA.
1
特長
2
アプリケーション
3
概要
ピン構成の概要
4
改訂履歴
5
Pin Configuration and Functions
Pin Functions
6
Specifications
6.1
Absolute Maximum Ratings
6.2
ESD Ratings
6.3
Recommended Operating Conditions
6.4
Thermal Information
6.5
Digital Input Electrical Characteristics – OE (SCL), INSEL, ITTP, OTTP, Divide (SDA/MOSI), ERC(ADDR/CS), Mode
6.6
Universal Input (IN1, IN2) Characteristics
6.7
Clock Output Buffer Characteristics (Output Mode = LVDS)
6.8
Clock Output Buffer Characteristics (Output Mode = HCSL)
6.9
Clock Output Buffer Electrical Characteristics (Output Mode = LVCMOS)
6.10
Clock Output Buffer Electrical Characteristics (Output Mode = LVCMOS) (Continued)
6.11
Clock Output Buffer Electrical Characteristics (Output Mode = LVCMOS) (Continued)
6.12
Typical Characteristics
7
Parameter Measurement Information
7.1
Test Configurations
8
Detailed Description
8.1
Overview
8.2
Functional Block Diagrams
8.3
Feature Description
8.3.1
Device Control Using Configuration Pins
8.3.1.1
Configuration of Output Type (OTTP)
8.3.1.2
Configuration of Edge Rate Control (ERC)
8.3.1.3
Control of Output Enable (OE)
8.3.2
Input Ports (IN1, IN2)
8.3.2.1
Configuration of the Input Type (ITTP)
8.3.2.2
Configuration of the IN2 Divider (INDIV)
8.3.3
Smart Input Multiplexer (INMUX)
8.3.3.1
Pin Configuration of the Smart Input Multiplexer (INMUX)
8.4
Device Functional Modes
8.4.1
Device Control Using the Host Interface
8.4.1.1
OE and INSEL in Host Configuration Mode
8.5
Programming
8.5.1
Host Interface Hardware Information
8.5.1.1
SPI Communication
8.5.1.1.1
CDCUN1208LP SPI Addressing
8.5.1.1.2
Writing to the CDCUN1208LP
8.5.1.1.3
Reading From the CDCUN1208LP
8.5.1.1.4
Block Write/Read Operation
8.5.1.2
I2C Communication
8.5.1.2.1
Message Transmission
8.5.1.2.1.1
Data and Address Bits
8.5.1.2.1.2
Special Symbols – Start (S) and Stop (P)
8.5.1.2.1.3
Special Symbols – Acknowledge (ACK)
8.5.1.2.1.4
Generic Message Frame
8.5.1.2.1.5
CDCUN1208LP Message Format
8.5.1.2.1.6
CDCUN1208LP Device Addressing (I2C Address)
8.5.1.2.1.7
CDCUN1208LP Device Addressing (Register Address)
8.5.1.2.2
I2C Master and Slave Handshaking
8.5.1.2.3
Block Read/Write
8.5.1.2.4
I2C Timing
8.6
Register Maps
8.6.1
Device Registers
8.6.1.1
Device Registers: Register 00-07
9
Application and Implementation
9.1
Application Information
9.2
Typical Application
9.2.1
PCI Express Applications
9.2.1.1
Design Requirements
9.2.1.2
Detailed Design Procedure
9.2.1.3
Application Curves
9.3
Systems Examples
10
Power Supply Recommendations
10.1
CDCUN1208LP Power Consumption
10.2
Device Power Supply Connections and Sequencing
10.3
Device Inputs (IN1, IN2)
11
Layout
11.1
Layout Guidelines
11.2
Layout Example
12
デバイスおよびドキュメントのサポート
12.1
ドキュメントの更新通知を受け取る方法
12.2
コミュニティ・リソース
12.3
商標
12.4
静電気放電に関する注意事項
12.5
Glossary
13
メカニカル、パッケージ、および注文情報
パッケージ・オプション
メカニカル・データ(パッケージ|ピン)
RHB|32
MPQF130D
サーマルパッド・メカニカル・データ
RHB|32
QFND029X
発注情報
jajsh89d_oa
jajsh89d_pm
9.2.1.3
Application Curves
Figure 42.
Output 1 (LVCMOS) Phase Noise With Clean 122.88-MHz Source
Figure 43.
Output 2 (LVCMOS) Phase Noise With Clean 122.88-MHz Source
(PN is Slightly Worse Due to the Mux and the Divider)