JAJSEY5 March   2018 CSD86336Q3D

PRODUCTION DATA.  

  1. 1特長
  2. 2アプリケーション
  3. 3概要
    1.     上面図
      1.      Device Images
  4. 4改訂履歴
  5. 5Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 Recommended Operating Conditions
    3. 5.3 Thermal Information
    4. 5.4 Power Block Performance
    5. 5.5 Electrical Characteristics – Q1 Control FET
    6. 5.6 Electrical Characteristics – Q2 Sync FET
    7. 5.7 Typical Power Block Device Characteristics
    8. 5.8 Typical Power Block MOSFET Characteristics
  6. 6Application and Implementation
    1. 6.1 Application Information
      1. 6.1.1 Equivalent System Performance
    2. 6.2 Power Loss Curves
    3. 6.3 Safe Operating Area (SOA) Curves
    4. 6.4 Normalized Curves
    5. 6.5 Calculating Power Loss and Safe Operating Area (SOA)
      1. 6.5.1 Design Example
      2. 6.5.2 Calculating Power Loss
      3. 6.5.3 Calculating SOA Adjustments
  7. 7Layout
    1. 7.1 Recommended Schematic Overview
    2. 7.2 Recommended PCB Design Overview
      1. 7.2.1 Electrical Performance
      2. 7.2.2 Thermal Performance
  8. 8デバイスおよびドキュメントのサポート
    1. 8.1 ドキュメントの更新通知を受け取る方法
    2. 8.2 コミュニティ・リソース
    3. 8.3 商標
    4. 8.4 静電気放電に関する注意事項
    5. 8.5 Glossary
  9. 9メカニカル、パッケージ、および注文情報
    1. 9.1 Q3Dパッケージの寸法
    2. 9.2 ピン構成
    3. 9.3 推奨ランド・パターン
    4. 9.4 推奨ステンシル

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

7.2.1 Electrical Performance

The power block has the ability to switch at voltage rates greater than 10 kV/μs. Special care must be taken with the PCB layout design and placement of the input capacitors, inductor, driver IC and output capacitors.

  • The placement of the input capacitors relative to the power block’s VIN and PGND pins should have the highest priority during the component placement routine. It is critical to minimize these node lengths. As such, ceramic input capacitors need to be placed as close as possible to the VIN and PGND pins (see Figure 33). It is recommended that one 3.3-nF (or similar), 0402, 50-V ceramic capacitor be placed on the top side of the board as close as possible to VIN and PGND pins. In addition, a minimum of 40 μF of bulk ceramic capacitance should be placed as close as possible to the power block in a design. For high-density design, some of these ceramic capacitors can be placed on the bottom layer of PCB with appropriate number of vias interconnecting both layers.
  • The driver IC should be placed relatively close to the power block gate pins. TG and BG should connect to the outputs of the driver IC. The TGR pin serves as the return path of the high-side gate drive circuitry and should be connected to the phase pin of the IC (sometimes called LX, LL, SW, PH, etc.). The bootstrap capacitor for the driver IC will also connect to this pin.
  • The switching node of the output inductor should be placed relatively close to the power block VSW pins. Minimizing the node length between these two components will reduce the PCB conduction losses and actually reduce the switching noise level. In the event the switch node waveform exhibits ringing that reaches undesirable levels, the use of a boost resistor or RC snubber can be an effective way to easily reduce the peak ring level. The recommended boost resistor value will range between 1.0 Ω to 4.7 Ω depending on the output characteristics of driver IC used in conjunction with the power block. The RC snubber values can range from 0.5 Ω to 2.2 Ω for the R and 330 pF to 2200 pF for the C. Please refer to Snubber Circuits: Theory, Design and Application (SLUP100) for more details on how to properly tune the RC snubber values. The RC snubber should be placed as close as possible to the VSW node and PGND (see Figure 33 and Figure 34). (1)
    • 1. Keong W. Kam, David Pommerenke, “EMI Analysis Methods for Synchronous Buck Converter EMI Root Cause Analysis”, University of Missouri – Rolla