JAJSEY5 March   2018 CSD86336Q3D

PRODUCTION DATA.  

  1. 1特長
  2. 2アプリケーション
  3. 3概要
    1.     上面図
      1.      Device Images
  4. 4改訂履歴
  5. 5Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 Recommended Operating Conditions
    3. 5.3 Thermal Information
    4. 5.4 Power Block Performance
    5. 5.5 Electrical Characteristics – Q1 Control FET
    6. 5.6 Electrical Characteristics – Q2 Sync FET
    7. 5.7 Typical Power Block Device Characteristics
    8. 5.8 Typical Power Block MOSFET Characteristics
  6. 6Application and Implementation
    1. 6.1 Application Information
      1. 6.1.1 Equivalent System Performance
    2. 6.2 Power Loss Curves
    3. 6.3 Safe Operating Area (SOA) Curves
    4. 6.4 Normalized Curves
    5. 6.5 Calculating Power Loss and Safe Operating Area (SOA)
      1. 6.5.1 Design Example
      2. 6.5.2 Calculating Power Loss
      3. 6.5.3 Calculating SOA Adjustments
  7. 7Layout
    1. 7.1 Recommended Schematic Overview
    2. 7.2 Recommended PCB Design Overview
      1. 7.2.1 Electrical Performance
      2. 7.2.2 Thermal Performance
  8. 8デバイスおよびドキュメントのサポート
    1. 8.1 ドキュメントの更新通知を受け取る方法
    2. 8.2 コミュニティ・リソース
    3. 8.3 商標
    4. 8.4 静電気放電に関する注意事項
    5. 8.5 Glossary
  9. 9メカニカル、パッケージ、および注文情報
    1. 9.1 Q3Dパッケージの寸法
    2. 9.2 ピン構成
    3. 9.3 推奨ランド・パターン
    4. 9.4 推奨ステンシル

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

7.2.2 Thermal Performance

The power block has the ability to utilize the GND planes as the primary thermal path. As such, the use of thermal vias is an effective way to pull away heat from the device and into the system board. Concerns of solder voids and manufacturability problems can be addressed by the use of three basic tactics to minimize the amount of solder attach that will wick down the via barrel:

  • Intentionally space out the vias from each other to avoid a cluster of holes in a given area.
  • Use the smallest drill size allowed in your design. The examples in Figure 33 and Figure 34 use vias with a 10-mil drill hole and a 16-mil capture pad.
  • Tent the opposite side of the via with solder-mask.

In the end, the number and drill size of the thermal vias should align with the end user’s PCB design rules and manufacturing capabilities.

CSD86336Q3D Top.gifFigure 33. Recommended PCB Layout (Top Down View)
CSD86336Q3D Bottom.gifFigure 34. Recommended PCB Layout (Bottom View)