JAJSI27A October 2019 – December 2019 DAC11001A , DAC81001 , DAC91001
UNLESS OTHERWISE NOTED, this document contains PRODUCTION DATA.
In synchronous mode (LDACMODE = 1), the LDAC pin is used as an active-low signal for simultaneous DAC updates. Data buffers must be loaded with the desired data before an LDAC low pulse. After an LDAC low pulse, the DAC is updated with the last contents of the corresponding data buffers. If the content of a data buffer is not changed, the DAC output remains unchanged after the LDAC pin is pulsed low.