JAJSNI4 December   2021 DAC11001B

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics
    6. 6.6  Timing Requirements: Write, 4.5 V ≤ DVDD ≤ 5.5 V
    7. 6.7  Timing Requirements: Write, 2.7 V ≤ DVDD < 4.5 V
    8. 6.8  Timing Requirements: Read and Daisy-Chain Write, 4.5 V ≤ DVDD ≤ 5.5 V
    9. 6.9  Timing Requirements: Read and Daisy-Chain Write, 2.7 V ≤ DVDD < 4.5 V
    10. 6.10 Timing Diagrams
    11. 6.11 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Digital-to-Analog Converter Architecture
      2. 7.3.2 External Reference
      3. 7.3.3 Output Buffers
      4. 7.3.4 Internal Power-On Reset (POR)
      5. 7.3.5 Temperature Drift and Calibration
      6. 7.3.6 DAC Output Deglitch Circuit
    4. 7.4 Device Functional Modes
      1. 7.4.1 Fast-Settling Mode and THD
      2. 7.4.2 DAC Update Rate Mode
    5. 7.5 Programming
      1. 7.5.1 Daisy-Chain Operation
      2. 7.5.2 CLR Pin Functionality and Software Clear
      3. 7.5.3 Output Update (Synchronous and Asynchronous)
        1. 7.5.3.1 Synchronous Update
        2. 7.5.3.2 Asynchronous Update
      4. 7.5.4 Software Reset Mode
    6. 7.6 Register Map
      1. 7.6.1 NOP Register (address = 00h) [reset = 0x000000h for bits [23:0]]
      2. 7.6.2 DAC-DATA Register (address = 01h) [reset = 0x000000h for bits [23:0]]
      3. 7.6.3 CONFIG1 Register (address = 02h) [reset = 004C80h for bits [23:0]]
      4. 7.6.4 DAC-CLEAR-DATA Register (address = 03h) [reset = 000000h for bits [23:0]]
      5. 7.6.5 TRIGGER Register (address = 04h) [reset = 000000h for bits [23:0]]
      6. 7.6.6 STATUS Register (address = 05h) [reset = 000000h for bits [23:0]]
      7. 7.6.7 CONFIG2 Register (address = 06h) [reset = 000040h for bits [23:0]]
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Source Measure Unit (SMU)
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
        3. 8.2.1.3 Application Curves
      2. 8.2.2 High-Precision Control Loop
        1. 8.2.2.1 Design Requirements
        2. 8.2.2.2 Detailed Design Procedure
        3. 8.2.2.3 Application Curves
      3. 8.2.3 Arbitrary Waveform Generation (AWG)
        1. 8.2.3.1 Design Requirements
        2. 8.2.3.2 Detailed Design Procedure
        3. 8.2.3.3 Application Curves
    3. 8.3 System Examples
      1. 8.3.1 Interfacing to a Processor
      2. 8.3.2 Interfacing to a Low-Jitter LDAC Source
      3. 8.3.3 Embedded Resistor Configurations
        1. 8.3.3.1 Minimizing Bias Current Mismatch
        2. 8.3.3.2 2x Gain Configuration
        3. 8.3.3.3 Generating Negative Reference
    4. 8.4 What to Do and What Not to Do
      1. 8.4.1 What to Do
      2. 8.4.2 What Not to Do
    5. 8.5 Initialization Set Up
  9. 9 Power Supply Recommendations
    1. 9.1 Power-Supply Sequencing
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 PCB Assembly Effects on Precision
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Development Support
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 Receiving Notification of Documentation Updates
    4. 11.4 サポート・リソース
    5. 11.5 Trademarks
    6. 11.6 Electrostatic Discharge Caution
    7. 11.7 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

6.11 Typical Characteristics

at TA = 25°C, VCC = 15 V, VSS = –15 V, AVDD = 5 V, IOVDD = 1.8 V, gain resistors unconnected (gain = 1x), OPA827 used as reference amplifier, OPA828 used as output amplifier, UP = unipolar, BP = bipolar, and temperature calibration disabled (unless otherwise noted)

 
Figure 6-3 Integral Linearity Error vs Digital Input Code
Figure 6-5 Integral Linearity Error vs Temperature
GUID-3C3B81AC-BDE4-44CF-A182-DA536C4D4445-low.gifFigure 6-7 Zero Code Error vs Temperature
GUID-06F2BFAD-1B62-409D-AF16-F34E7975C710-low.gifFigure 6-9 Gain Error vs Temperature
GUID-978951FB-110F-457E-8B3D-4B67243C0A15-low.gif
 
Figure 6-11 Differential Linearity Error vs Supply Voltage
GUID-D7CC87D5-09DC-4DF3-B2BC-D2462C281D67-low.gif
 
Figure 6-13 Positive Full-Scale Error vs Supply Voltage
GUID-5B6B6324-EE7A-4710-87DB-68E1708B661F-low.gif
 
Figure 6-15 Integral Linearity Error vs Reference Voltage
GUID-4CCBA51E-DD62-495C-9B53-87D179452C08-low.gif
 
Figure 6-17 Zero Code Error vs Reference Voltage
GUID-6351479A-8F21-4DA6-BDF0-29CDBCF82D18-low.gif
 
Figure 6-19 Positive Full-Scale Error vs Reference Voltage
VREFPF = 10 V, VREFNF = 0 V
Figure 6-21 Supply Current (VCC and VSS)
vs Digital Input Code
VREFPF = 10 V, VREFNF = 0 V
Figure 6-23 Supply Current (AVDD) vs Digital Input Code
VREFPF = 10 V, VREFNF = 0 V, DAC at midcode
Figure 6-25 Supply Current (VCC and VSS)
vs Temperature
VREFPF = 10 V, VREFNF = 0 V, DAC at midcode
 
Figure 6-27 Supply Current (AVDD) vs Temperature
VREFPF = 10 V, VREFNF = 0 V, DAC at midcode
Figure 6-29 Supply Current (IOVDD)
vs Input Pin Logic Level
GUID-F63DD036-0092-4782-9C7F-21ED474CD36D-low.gif
VREFPF = 10 V, VREFNF = –10 V,
DAC transition midcode – 1 to midcode
Figure 6-31 Glitch Impulse, Rising Edge, 1-LSB Step
GUID-E109E5E5-DBEA-4A9C-80AB-782C4D0A82AE-low.gif
VREFPF = 10 V, VREFNF = –10 V
Figure 6-33 Segment Glitch Impulse, 1-LSB Step
GUID-C99B5221-4E87-4D10-B944-EB05ECE71C5D-low.gif
VREFPF = 5 V, VREFNF = 0 V
Figure 6-35 Segment Glitch Impulse, 1-LSB Step
GUID-246948A9-8812-4EF2-A5CE-A172599FED89-low.gif
VREFPF = 10 V, VREFNF = 0 V
Figure 6-37 Full-Scale Settling Time, Rising Edge
GUID-0EAAA1DC-3CD7-4ABF-8290-9C1D37039DA4-low.gif
VREFPF = 10 V, VREFNF = 0 V,
DAC transitions 100 codes around midscale
Figure 6-39 100 Codes Settling Time, Rising Edge
GUID-3889AF95-678D-4325-9F7A-51D8EE0DD4FD-low.gif
VREFPF = 10 V, VREFNF = 0 V, measured at DAC output
Figure 6-41 DAC Output Noise Spectral Density
DAC update rate = 768 kHz, VREFPF = 4.5 V, VREFNF = −4.5 V, sixth-order, low-pass, 30-kHz output filter
Figure 6-43 1-kHz Spectrum vs Frequency
DAC update rate = 1 MHz, VREFPF = 4.5 V, VREFNF = −4.5 V, sixth-order, low-pass, 150-kHz output filter
Figure 6-45 100-kHz Spectrum vs Frequency
DAC update rate = 768 kHz, VREFPF = 4.5 V, VREFNF = −4.5 V, sixth-order, low-pass, 30-kHz output filter
Figure 6-47 Total Harmonic Distortion
vs Output Frequency, fDAC = 768 kHz
DAC update rate = 768 kHz, VREFPF = 4.5 V, VREFNF = −4.5 V, sixth-order, low-pass, 30-kHz output filter
Figure 6-49 Second Harmonic Distortion
vs Output Frequency, fDAC = 768 kHz
DAC update rate = 1 MHz, VREFPF = 4.5 V, VREFNF = −4.5 V, sixth-order, low-pass, 150-kHz output filter
Figure 6-51 Spurious Free Dynamic Range
vs Output Frequency, fDAC = 1 MHz
DAC update rate = 1 MHz, VREFPF = 4.5 V, VREFNF = −4.5 V, sixth-order, low-pass, 150-kHz output filter
Figure 6-53 Total Harmonic Distortion + Noise
vs Output Frequency, fDAC = 1 MHz
DAC update rate = 1 MHz, VREFPF = 4.5 V, VREFNF = −4.5 V, sixth-order, low-pass, 150-kHz output filter
Figure 6-55 Third Harmonic Distortion
vs Output Frequency, fDAC = 1 MHz
DAC output frequency = 20 kHz, VREFPF = 4.5 V, VREFNF = −4.5 V, sixth-order, low-pass, 30-kHz output filter
Figure 6-57 Total Harmonic Distortion vs Update Rate
DAC output frequency = 20 kHz, VREFPF = 4.5 V, VREFNF = −4.5 V, sixth-order, low-pass, 30-kHz output filter
Figure 6-59 Second Harmonic Distortion vs Update Rate
 
Figure 6-4 Differential Linearity Error vs Digital Input Code
Figure 6-6 Differential Linearity Error vs Temperature
GUID-AAEA653A-7BC4-429C-9010-92F007F3AA24-low.gifFigure 6-8 Positive Full-Scale Error vs Temperature
GUID-FEB1F33E-DC35-4ABA-A4F0-043BB476F935-low.gif
 
Figure 6-10 Integral Linearity Error vs Supply Voltage
GUID-521D959D-8906-4D7C-9207-0BEDBC9D46BC-low.gif
 
Figure 6-12 Zero Code Error vs Supply Voltage
GUID-4C7D1310-6134-44DF-89EC-10BCDC7102A8-low.gif
 
Figure 6-14 Gain Error vs Supply Voltage
GUID-C4BC7041-20E6-4BDC-B170-B41FB8EBF193-low.gif
 
Figure 6-16 Differential Linearity Error vs Reference Voltage
GUID-477A92CE-E57B-4E6C-9CFA-F52B054C776E-low.gif
 
Figure 6-18 Gain Error vs Reference Voltage
VREFPF = 10 V, VREFNF = 0 V
Figure 6-20 Supply Current (DVDD and IOVDD) vs Digital Input Code
VREFPF = 10 V, VREFNF = 0 V
Figure 6-22 Reference Current (VREFPF and VREFNF) vs Digital Input Code
VREFPF = 10 V, VREFNF = 0 V, DAC at midcode
Figure 6-24 Supply Current (DVDD) vs Temperature
VREFPF = 10 V, VREFNF = 0 V, DAC at midcode
Figure 6-26 Reference Current (VREFPF and VREFNF)
vs Temperature
VREFPF = 5 V, VREFNF = 0 V, DAC at midcode
Figure 6-28 Supply Current (VCC and VSS) vs Supply Voltage
VREFPF = 10 V, VREFNF = 0 V, DAC at midcode
Figure 6-30 Supply Current (IOVDD)
vs Input Pin Logic Level
GUID-159CDCDB-9339-4D85-A914-A469E5AA7F28-low.gif
VREFPF = 10 V, VREFNF = –10 V,
DAC transition midcode to midcode – 1
Figure 6-32 Glitch Impulse, Falling Edge, 1-LSB Step
GUID-D93D2BBE-A087-4099-B85C-6EF447E0B33E-low.gif
VREFPF = 10 V, VREFNF = 0 V
Figure 6-34 Segment Glitch Impulse, 1-LSB Step
GUID-B7BCF12E-2A58-43E5-918A-B6263751FD80-low.gif
VREFPF = 10 V, VREFNF = 0 V,
DAC at midcode, measured at DAC output pin
Figure 6-36 Clock Feedthrough
GUID-DBEE5EBA-CFDE-4DC7-9793-4BE8D403F6B6-low.gif
VREFPF = 10 V, VREFNF = 0 V
 
Figure 6-38 Full-Scale Settling Time, Falling Edge
GUID-51A35A81-7F56-4751-B29D-D788EC1DE1F2-low.gif
VREFPF = 10 V, VREFNF = 0 V,
DAC transitions 100 codes around midscale
Figure 6-40 100 Codes Settling Time, Falling Edge
GUID-35C0815A-DB49-4B76-B3FC-E0E6956A000E-low.gif
VREFPF = 10 V, VREFNF = 0 V,
DAC at midcode, measured at DAC output pin
Figure 6-42 DAC Output Noise: 0.1 Hz to 10 Hz
DAC update rate = 768 kHz, VREFPF = 4.5 V, VREFNF = −4.5 V, sixth-order, low-pass, 30-kHz output filter
Figure 6-44 20-kHz Spectrum vs Frequency
DAC update rate = 768 kHz, VREFPF = 4.5 V, VREFNF = −4.5 V, sixth-order, low-pass, 30-kHz output filter
Figure 6-46 Spurious Free Dynamic Range
vs Output Frequency, fDAC = 768 kHz
DAC update rate = 768 kHz, VREFPF = 4.5 V, VREFNF = −4.5 V, sixth-order, low-pass, 30-kHz output filter
Figure 6-48 Total Harmonic Distortion + Noise
vs Output Frequency, fDAC = 768 kHz
DAC update rate = 768 kHz, VREFPF = 4.5 V, VREFNF = −4.5 V, sixth-order, low-pass, 30-kHz output filter
Figure 6-50 Third Harmonic Distortion
vs Output Frequency, fDAC = 768 kHz
DAC update rate = 1 MHz, VREFPF = 4.5 V, VREFNF = −4.5 V, sixth-order, low-pass, 150-kHz output filter
Figure 6-52 Total Harmonic Distortion
vs Output Frequency, fDAC = 1 MHz
DAC update rate = 1 MHz, VREFPF = 4.5 V, VREFNF = −4.5 V, sixth-order, low-pass, 150-kHz output filter
Figure 6-54 Second Harmonic Distortion
vs Output Frequency, fDAC = 1 MHz
DAC output frequency = 20 kHz, VREFPF = 4.5 V, VREFNF = −4.5 V, sixth-order, low-pass, 30-kHz output filter
Figure 6-56 Spurious Free Dynamic Range vs Update Rate
DAC output frequency = 20 kHz, VREFPF = 4.5 V, VREFNF = −4.5 V, sixth-order, low-pass, 30-kHz output filter
Figure 6-58 Total Harmonic Distortion + Noise vs Update Rate
DAC output frequency = 20 kHz, VREFPF = 4.5 V, VREFNF = −4.5 V, sixth-order, low-pass, 30-kHz output filter
Figure 6-60 Third Harmonic Distortion vs Update Rate