9.1 Power-up Sequence

The following startup sequence is recommended to power-up the DAC3282:

1. Set TXENABLE low.
2. Supply all 1.8V voltages (DACVDD, DIGVDD, CLKVDD and VFUSE) and all 3.3V voltages (AVDD). The 1.8V and 3.3V supplies can be powered up simultaneously or in any order. There are no specific requirements on the ramp rate for the supplies.
3. Provide all LVPECL inputs: DACCLKP/N and the optional OSTRP/N. These inputs can also be provided after the SIF register programming.
4. Toggle the RESETB pin for a minimum of 25ns active low pulse width.
5. Program all the SIF registers.
6. FIFO configuration needed for synchronization:
   1. Program fifo_reset_ena (config0, bit<5>) to enable FRAMEP/N as the FIFO input pointer sync source.
   2. Program multi_sync_ena (config0, bit<4>) to enable syncing of the FIFO output pointer.
   3. Program multi_sync_sel (config19, bit<1>) to select the FIFO output pointer and clock divider sync source
7. Clock divider configuration needed for synchronization:
   1. Program clkdiv_sync_ena (config18, bit<1>) to “1” to enable clock divider sync.
8. Provide all LVDS inputs (D[7:0]P/N, DATACLKP/N, and FRAMEP/N) simultaneously. Synchronize the FIFO and clock divider by providing the pulse or periodic signals needed.
   1. For Single Sync Source Mode where FRAMEP/N is used to sync the FIFO, a single rising edge for FIFO, FIFO data formatter, and clock divider sync is recommended. Periodic sync signal is not recommended due to the non-deterministic latency of the sync signal through the clock domain transfer.
   2. For Dual Sync Sources Mode, both single pulse or periodic sync signals can be used.
9. FIFO and clock divider configurations after all the sync signals have provided the initial sync pulses needed for synchronization:
   1. For Single Sync Source Mode where the clock divider sync source is FRAMEP/N, clock divider syncing may be disabled after DAC3282 initialization and before the data transmission by setting clkdiv_sync_ena (config18, bit<1>) to “0”. This is to prevent accidental syncing of the clock divider when sending FRAMEP/N pulse to other digital blocks.
   2. For Dual Sync Sources Mode, where the clock divider sync source is from the OSTRP/N, the clock divider syncing may be enabled at all time.
   3. Optionally, to prevent accidental syncing of the FIFO, disable FIFO syncing by setting fifo_reset_ena and multi_sync_ena to “0” after the FIFO input and output pointers are initialized. If the FIFO sync remains enabled after initialization, the FRAMEP/N pulse must occur in ways to not disturb the FIFO operation. Refer to the Input FIFO section for detail.
10. Enable transmit of data by asserting the TXENABLE pin.
11. At all time, if any of the clocks (i.e. DATACLK or DACCLK) is lost or FIFO collision alarm is detected, a complete resynchronization of the DAC is necessary. Please set TXENABLE low and repeat step 6 through 10. Program the FIFO configuration and clock divider configuration per step 6 and 7 appropriately to accept the new sync pulse or pulses for the synchronization.