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JAJSCY4D December 2016 – December 2023 DAC38RF80 , DAC38RF83 , DAC38RF84 , DAC38RF85 , DAC38RF90 , DAC38RF93

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7.3.12 SerDes Test Modes through IEEE 1500 Programming

DAC38RFxx also provide a number of advanced diagnostic capabilities controlled by the IEEE 1500 interface. These are:

Accumulation of pattern verification errors;
The ability to map out the width and height of the receive eye, known as Eye Scan;
Rreal-time monitoring of internal voltages and currents;
The SerDes blocks support the following IEEE1500 instructions:

Table 7-24 IEEE1500 Instruction for SerDes Receivers

INSTRUCTION	OPCODE	DESCRIPTION
ws_bypass	0x00	Bypass. Selects a 1-bit bypass data register. Use when accessing other macros on the same IEEE1500 scan chain.
ws_cfg	0x35	Configuration. Write protection options for other instructions.
ws_core	0x30	Core. Fields also accessible through dedicated core-side ports.
ws_tuning	0x31	Tuning. Fields for fine tuning macro performance.
ws_debug	0x32	Debug. Fields for advanced control, manufacturing test, silicon characterization and debug.
ws_unshadowed	0x34	Unshadowed. Fields for silicon characterization.
ws_char	0x33	Char. Fields used for eye scan.

The data for each SerDes instruction is formed by chaining together sub-components called head, body (receiver or transmitter) and tail. DAC38RFxx uses two SerDes receiver blocks R0 and R1, each of which contains 4 receive lanes (channels), the data for each IEEE1500 instruction is formed by chaining {head, receive lane 0, receive lane 1, receive lane 2, receive lane 3, tail}. A description of bits in head, body and tail for each instruction is given as follows:

Note:

All multi-bit signals in each chain are packed with bits reversed for example, mpy[7:0] in ws_core head subchain is packed as {retime, enpll, mpy[0:7], vrange, lb[0:1]}. All DATA REGISTER READS from SerDes Block R0 should read 1 bit more than the desired number of bits and discard the first bit received on TDO for example,, to read 40-bit data from R0 block, 41 bits should be read off from TDO and the first bit received should be discarded. Similarly, any data written to SerDes Block R0 Data Registers should be prefixed with an extra 0.

Table 7-25 ws_cfg Chain

FIELD	DESCRIPTION
HEAD (STARTING FROM THE MSB OF CHAIN)
RETIME	No function.
CORE_WE	Core chain write enable.
RECEIVER (FOR EACH LANE 0, 1, 2, 3)
CORE_WE	Core chain write enable.
TUNING_WE	Tuning chain write enable.
DEBUG_WE	Reserved.
CHAR_WE	Char chain write enable.
UNSHADOWED_WE	Reserved.
TAIL (ENDING WITH THE LSB OF CHAIN)
CORE_WE	Core chain write enable.
TUNING_WE	Tuning chain write enable.
DEBUG_WE	Reserved.
RETIME	No function.
CHAIN LENGTH = 26 BITS

Table 7-26 ws_core Chain

FIELD	DESCRIPTION
HEAD (STARTING FROM THE MSB OF CHAIN)
RETIME	No function.
ENPLL	PLL enable.
MPY[7:0]	PLL multiply.
VRANGE	VCO range.
ENDIVCLK	Enable DIVCLK output
LB[1:0]	Loop bandwidth
RECEIVER (FOR EACH LANE 0,1,2,3)
ENRX	Receiver enable.
SLEEPRX	Receiver sleep mode.
BUSWIDTH[2:0]	Bus width.
RATE[1:0]	Operating rate.
INVPAIR	Invert polarity.
TERM[2:0]	Termination.
ALIGN[1:0]	Symbol alignment.
LOS[2:0]	Loss of signal enable.
CDR[2:0]	Clock/data recovery.
EQ[2:0]	Equalizer.
EQHLD	Equalizer hold.
ENOC	Offset compensation.
LOOPBACK[1:0]	Loopback.
BSINRXP	Boundary scan initialization.
BSINRXN	Boundary scan initialization.
RESERVED	Reserved.
Testpatt[2:0]	Test pattern selection.
TESTFAIL	Test failure (real time).
LOSTDTCT	Loss of signal detected (real time).
BSRXP	Boundary scan data.
BSRXN	Boundary scan data.
OCIP	Offset compensation in progress.
EQOVER	Receiver signal over equalized.
EQUNDER	Receiver signal under equalized.
LOSTDTCT	Loss of signal detected (sticky).
SYNC	Re-alignment done, or aligned comma output (sticky).
RETIME	No function.
TAIL (ENDING WITH THE LSB CHAIN)
CLKBYP[1:0]	Clock bypass.
SLEEPPLL	PLL sleep mode.
RESERVED	Reserved.
LOCK	PLL lock (real time).
BSINITCLK	Boundary scan initialization clock.
ENBSTX	Enable TX boundary scan.
ENBSRX	Enable RX boundary scan.
ENBSPT	RX pulse boundary scan.
RESERVED	Reserved.
NEARLOCK	PLL near to lock.
UNLOCK	PLL lock (sticky).
CFG OVR	Configuration over-ride.
RETIME	No function.
CHAIN LENGTH = 196 BITS

Table 7-27 ws_tuning Chain

FIELD	DESCRIPTION
HEAD (STARTING FROM THE MSB OF CHAIN)
RETIME	No function.
RECEIVER (FOR EACH LANE 0,1,2,3)
PATTERRTHR[2:0]	Resync error threshold.
PATT TIMER	PRBS timer.
RXDSEL[3:0]	Status select.
ENCOR	Enable clear-on-read for error counter.
EQZERO[4:0]	EQZ OVRi Equalizer zero.
EQZ OVR	Equalizer zero over-ride.
EQLEVEL[15:0]	EQ OVRi Equalizer gain observe or set.
EQ OVR	Equalizer over-ride.
EQBOOST[1:0]	Equalizer gain boost.
RXASEL[2:0]	Selects amux output.
TAIL (ENDING WITH THE LSB CHAIN)
ASEL[3:0]	Selects amux output.
USR PATT[19:0]	User-defined test pattern.
RETIME	No function.
CHAIN LENGTH = 174 BITS

Table 7-28 ws_char Chain

FIELD	DESCRIPTION
HEAD (STARTING FROM THE MSB OF CHAIN)
RETIME	No function.
RECEIVER (FOR EACH LANE 0,1,2,3)
TESTFAIL	Test failure (sticky).
ECOUNT[11:0]	Error counter.
ESWORD[7:0]	Eye scan word masking.
ES[3:0]	Eye scan.
ESPO[6:0]	Eye scan phase offset.
ES BIT SELECT[4:0]	Eye scan compare bit select.
ESVO[5:0]	Eye scan voltage offset.
ESVO OVR	Eye scan voltage offset override.
ESLEN[1:0]	Eye scan run length.
ESRUN	Eye scan run.
ESDONE	Eye scan done.
TAIL (ENDING WITH THE LSB CHAIN)
RETIME	No function.
CHAIN LENGTH = 194 BITS