JAJSCY4D December   2016  – December 2023 DAC38RF80 , DAC38RF83 , DAC38RF84 , DAC38RF85 , DAC38RF90 , DAC38RF93

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Device Comparison
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics - DC Specifications
    6. 6.6  Electrical Characteristics - Digital Specifications
    7. 6.7  Electrical Characteristics - AC Specifications
    8. 6.8  PLL/VCO Electrical Characteristics
    9. 6.9  Timing Requirements
    10. 6.10 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagrams
    3. 7.3 Feature Description
      1. 7.3.1  SerDes Inputs
      2. 7.3.2  SerDes Rate
      3. 7.3.3  SerDes PLL
      4. 7.3.4  SerDes Equalizer
      5. 7.3.5  JESD204B Descrambler
      6. 7.3.6  JESD204B Frame Assembly
      7. 7.3.7  SYNC Interface
      8. 7.3.8  Single or Dual Link Configuration
      9. 7.3.9  Multi-Device Synchronization
      10. 7.3.10 SYSREF Capture Circuit
      11. 7.3.11 SerDes Test Modes through Serial Programming
      12. 7.3.12 SerDes Test Modes through IEEE 1500 Programming
      13. 7.3.13 Error Counter
      14. 7.3.14 Eye Scan
      15. 7.3.15 JESD204B Pattern Test
      16. 7.3.16 Multiband DUC (multi-DUC)
        1. 7.3.16.1 Multi-DUC input
        2. 7.3.16.2 Interpolation Filters
        3. 7.3.16.3 JESD204B Modes, Interpolation and Clock phase Programming
        4. 7.3.16.4 Digital Quadrature Modulator
        5. 7.3.16.5 Low Power Coarse Resolution Mixing Modes
        6. 7.3.16.6 Inverse Sinc Filter
        7. 7.3.16.7 Summation Block for Dual DUC Modes
      17. 7.3.17 PA Protection Block
      18. 7.3.18 Gain Block
      19. 7.3.19 Output Summation
      20. 7.3.20 Output Delay
      21. 7.3.21 Polarity Inversion
      22. 7.3.22 Temperature Sensor
      23. 7.3.23 Alarm Monitoring
      24. 7.3.24 Differential Clock Inputs
      25. 7.3.25 CMOS Digital Inputs
      26. 7.3.26 DAC Fullscale Output Current
      27. 7.3.27 Current Steering DAC Architecture
      28. 7.3.28 DAC Transfer Function for DAC38RF83, 93, 85
      29. 7.3.29 DAC Transfer Function for DAC38RF80/90/84
    4. 7.4 Device Functional Modes
      1. 7.4.1 Clocking Modes
      2. 7.4.2 PLL Bypass Mode Programming
      3. 7.4.3 Internal PLL/VCO
      4. 7.4.4 CLKOUT
      5. 7.4.5 Serial Peripheral Interface (SPI)
        1. 7.4.5.1 NORMAL (RW)
        2. 7.4.5.2 WRITE_TO_CLEAR (W0C)
        3. 7.4.5.3 Writing to Reserved Bits
    5. 7.5 Register Maps
      1. 7.5.1  Chip Reset and Configuration Register (address = 0x00) [reset = 0x5803]
      2. 7.5.2  IO Configuration Register (address = 0x01) [reset = 0x1800]
      3. 7.5.3  Lane Single Detect Alarm Mask Register (address = 0x02) [reset = 0xFFFF]
      4. 7.5.4  Clock Alarms Mask Register (address = 0x03) [reset = 0xFFFF
      5. 7.5.5  SERDES Loss of Signal Detection Alarms Register (address = 0x04) [reset = 0x0000]
      6. 7.5.6  SYSREF Alignment Circuit Alarms Register (address = 0x05) [reset = variable]
      7. 7.5.7  Temperature Sensor and PLL Loop Voltage Register (address = 0x06) [reset = variable]
      8. 7.5.8  Page Set Register (address = 0x09) [reset = 0x0000]
      9. 7.5.9  SYSREF Align to r1 and r3 Count Register (address = 0x78) [reset = 0x0000]
      10. 7.5.10 SYSREF Phase Count 1 and 2 Register (address = 0x79) [reset = 0x0000]
      11. 7.5.11 SYSREF Phase Count 3 and 4 Register (address = 0x7A) [reset = 0x0000]
      12. 7.5.12 Vendor ID and Chip Version Register (address = 0x7F) [reset = 0x0009]
      13. 7.5.13 Multi-DUC Configuration (PAP, Interpolation) Register (address = 0x0A) [reset = 0x02B0]
      14. 7.5.14 Multi-DUC Configuration (Mixers) Register (address = 0x0C) [reset = 0x2402]
      15. 7.5.15 JESD FIFO Control Register (address = 0x0D)[reset = 0x8000]
      16. 7.5.16 Alarm Mask 1 Register (address = 0x0E) [reset = 0x00FF]
      17. 7.5.17 Alarm Mask 2 Register (address = 0x0F) [reset = 0xFFFF]
      18. 7.5.18 Alarm Mask 3 Register (address = 0x10) [reset = 0xFFFF]
      19. 7.5.19 Alarm Mask 4 Register (address = 0x11) [reset = 0xFFFF]
      20. 7.5.20 JESD Lane Skew Register (address = 0x12) [reset = 0x0000]
      21. 7.5.21 CMIX Configuration Register (address = 0x17) [reset = 0x0000]
      22. 7.5.22 Output Summation and Delay Register (address = 0x19) [reset = 0x0000]
      23. 7.5.23 NCO Phase Path AB Register (address = 0x1C) [reset = 0x0000]
      24. 7.5.24 NCO Phase Path CD Register (address = 0x1D) [reset = 0x0000]
      25. 7.5.25 NCO Frequency Path AB Register (address = 0x1E-0x20) [reset = 0x0000 0000 0000]
      26. 7.5.26 NCO Frequency Path CD Register (address = 0x21-0x23) [reset = 0x0000 0000 0000]
      27. 7.5.27 SYSREF Use for Clock Divider Register (address = 0x24) [reset = 0x0010]
      28. 7.5.28 Serdes Clock Control Register (address = 0x25) [reset = 0x7700]
      29. 7.5.29 Sync Source Control 1 Register (address = 0x27) [reset = 0x1144]
      30. 7.5.30 Sync Source Control 2 Register (address = 0x28) [reset = 0x0000]
      31. 7.5.31 PAP path AB Gain Attenuation Step Register (address = 0x29) [reset = 0x0000]
      32. 7.5.32 PAP path AB Wait Time Register (address = 0x2A) [reset = 0x0000]
      33. 7.5.33 PAP path CD Gain Attenuation Step Register (address = 0x2B) [reset = 0x0000]
      34. 7.5.34 PAP Path CD Wait Time Register (address = 0x2C) [reset = 0x0000]
      35. 7.5.35 PAP path AB Configuration Register (address = 0x2D) [reset = 0x0FFF]
      36. 7.5.36 PAP path CD Configuration Register (address = 0x2E) [reset = 0x0FFF]
      37. 7.5.37 DAC SPI Configuration Register (address = 0x2F) [reset = 0x0000]
      38. 7.5.38 DAC SPI Constant Register (address = 0x30) [reset = 0x0000]
      39. 7.5.39 Gain for path AB Register (address = 0x32) [reset = 0x0400]
      40. 7.5.40 Gain for path CD Register (address = 0x33) [reset = 0x0400]
      41. 7.5.41 JESD Error Counter Register (address = 0x41) [reset = 0x0000]
      42. 7.5.42 JESD ID 1 Register (address = 0x46) [reset = 0x0044]
      43. 7.5.43 JESD ID 2 Register (address = 0x47) [reset = 0x190A]
      44. 7.5.44 JESD ID 3 and Subclass Register (address = 0x48) [reset = 0x31C3]
      45. 7.5.45 JESD Lane Enable Register (address = 0x4A) [reset = 0x0003]
      46. 7.5.46 JESD RBD Buffer and Frame Octets Register (address = 0x4B) [reset = 0x1300]
      47. 7.5.47 JESD K and L Parameters Register (address = 0x4C) [reset = 0x1303]
      48. 7.5.48 JESD M and S Parameters Register (address = 0x4D) [reset = 0x0100]
      49. 7.5.49 JESD N, HD and SCR Parameters Register (address = 0x4E) [reset = 0x0F4F]
      50. 7.5.50 JESD Character Match and Other Register (address = 0x4F) [reset = 0x1CC1]
      51. 7.5.51 JESD Link Configuration Data Register (address = 0x50) [reset = 0x0000]
      52. 7.5.52 JESD Sync Request Register (address = 0x51) [reset = 0x00FF]
      53. 7.5.53 JESD Error Output Register (address = 0x52) [reset = 0x00FF]
      54. 7.5.54 JESD ILA Check 1 Register (address = 0x53) [reset = 0x0100]
      55. 7.5.55 JESD ILA Check 2 Register (address = 0x54) [reset = 0x8E60]
      56. 7.5.56 JESD SYSREF Mode Register (address = 0x5C) [reset = 0x0001]
      57. 7.5.57 JESD Crossbar Configuration 1 Register (address = 0x5F) [reset = 0x0123]
      58. 7.5.58 JESD Crossbar Configuration 2 Register (address = 0x60) [reset = 0x4567]
      59. 7.5.59 JESD Alarms for Lane 0 Register (address = 0x64) [reset = 0x0000]
      60. 7.5.60 JESD Alarms for Lane 1 Register (address = 0x65) [reset = 0x0000]
      61. 7.5.61 JESD Alarms for Lane 2 Register (address = 0x66) [reset = 0x0000]
      62. 7.5.62 JESD Alarms for Lane 3 Register (address = 0x67) [reset = 0x0000]
      63. 7.5.63 JESD Alarms for Lane 4 Register (address = 0x68) [reset = 0x0000]
      64. 7.5.64 JESD Alarms for Lane 5 Register (address = 0x69) [reset = 0x0000]
      65. 7.5.65 JESD Alarms for Lane 6 Register (address = 0x6A [reset = 0x0000]
      66. 7.5.66 JESD Alarms for Lane 7 Register (address = 0x6B) [reset = 0x0000]
      67. 7.5.67 SYSREF and PAP Alarms Register (address = 0x6C) [reset = 0x0000]
      68. 7.5.68 Clock Divider Alarms 1 Register (address = 0x6D) [reset = 0x0000]
      69. 7.5.69 Clock Configuration Register (address = 0x0A) [reset = 0xFC03]
      70. 7.5.70 Sleep Configuration Register (address = 0x0B) [reset = 0x0022]
      71. 7.5.71 Divided Output Clock Configuration Register (address = 0x0C) [reset = 0x2002]
      72. 7.5.72 DAC Fullscale Current Register (address = 0x0D) [reset = 0xF000]
      73. 7.5.73 Internal SYSREF Generator Register (address = 0x10) [reset = 0x0000]
      74. 7.5.74 Counter for Internal SYSREF Generator Register (address = 0x11) [reset = 0x0000]
      75. 7.5.75 SPI SYSREF for Internal SYSREF Generator Register (address = 0x12) [reset = 0x0000]
      76. 7.5.76 Digital Test Signals Register (address = 0x1B) [reset = 0x0000]
      77. 7.5.77 Sleep Pin Control Register (address = 0x23) [reset = 0xFFFF]
      78. 7.5.78 SYSREF Capture Circuit Control Register (address = 0x24) [reset = 0x1000]
      79. 7.5.79 Clock Input and PLL Configuration Register (address = 0x31) [reset = 0x0200]
      80. 7.5.80 PLL Configuration 1 Register (address = 0x32) [reset = 0x0308]
      81. 7.5.81 PLL Configuration 2 Register (address = 0x33) [reset = 0x4018]
      82. 7.5.82 LVDS Output Configuration Register (address = 0x34) [reset = 0x0000]
      83. 7.5.83 Fuse Farm clock divider Register (address = 0x35) [reset = 0x0018]
      84. 7.5.84 Serdes Clock Configuration Register (address = 0x3B) [reset = 0x1802]
      85. 7.5.85 Serdes PLL Configuration Register (address = 0x3C) [reset = 0x8228]
      86. 7.5.86 Serdes Configuration 1 Register (address = 0x3D) [reset = 0x0x0088]
      87. 7.5.87 Serdes Configuration 2 Register (address = 0x3E) [reset = 0x0x0909]
      88. 7.5.88 Serdes Polarity Control Register (address = 0x3F) [reset = 0x0000]
      89. 7.5.89 JESD204B SYNCB OUTPUT Register (address = 0x76) [reset = 0x0000]
  9. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Start-up Sequence
    2. 8.2 Typical Application: Multi-band Radio Frequency Transmitter
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Calculating the JESD204B SerDes Rate
        2. 8.2.2.2 Calculating valid JESD204B SYSREF Frequency
      3. 8.2.3 Application Curves
    3. 8.3 Power Supply Recommendations
      1. 8.3.1 Power Supply Sequencing
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 ドキュメントの更新通知を受け取る方法
    2. 9.2 サポート・リソース
    3. 9.3 Trademarks
    4. 9.4 静電気放電に関する注意事項
    5. 9.5 用語集
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

パッケージ・オプション

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メカニカル・データ（パッケージ｜ピン）
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発注情報

7.5.45 JESD Lane Enable Register (address = 0x4A) [reset = 0x0003]

Figure 7-78 JESD Lane Enable Register (JESD_LN_EN)
15141312111098
0000000x
R/WR/WR/WR/WR/WR/WR/WR/W
76543210
01001010
R/WR/WR/WR/WR/WR/WR/WR/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 7-88 JESD_LN_EN Field Descriptions
BitFieldTypeResetDescription
15:8LANE_ENA0x00Turn on each lane as needed. Signal is active high.
bit 15 : lane7 enable
bit 14 : lane6 enable
bit 13 : lane5 enable
bit 12 : lane4 enable
bit 11 : lane3 enable
bit 10 : lane2 enable
bit 9 : lane1 enable
bit 8 : lane0 enable
7:6JESD_TEST_SEQ00Set to select and verify link layer test sequences. The error for these sequences comes out the lane alarms bit0. 1= a fail and 0 = pass.
00 : test sequence disabled
01 : verify repeating D.21.5 high frequency pattern for random jitter
10 : verify repeating K.28.5 mixed frequency pattern for deterministic jitter
11 : verify repeating ILA sequence
5:2Reserved0x0Reserved
1:0JESD_PHASE_MODE11Used to tell the JESD block how many clock phases are being used for lanes.
00 = 1 phase
01 = 2 phases
10 = 4 phases
11 = 8 phases