JAJSDO4C February   2017  – April 2020 DAC38RF82 , DAC38RF89

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     32rep%#215;6MHz、256QAM の搬送波
  4. 4 改訂履歴
  5. 5 概要（続き）
  6. 6 Device Comparison Table
  7. 7 Pin Configuration and Functions
    1.     Pin Functions
  8. 8 Specifications
    1. 8.1  Absolute Maximum Ratings
    2. 8.2  ESD Ratings
    3. 8.3  Recommended Operating Conditions
    4. 8.4  Thermal Information
    5. 8.5  Electrical Characteristics - DC Specifications
    6. 8.6  Electrical Characteristics - Digital Specifications
    7. 8.7  Electrical Characteristics - AC Specifications
    8. 8.8  PLL/VCO Electrical Characteristics
    9. 8.9  Timing Requirements
    10. 8.10 Typical Characteristics
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagrams
    3. 9.3 Feature Description
      1. 9.3.1  SerDes Inputs
      2. 9.3.2  SerDes Rate
      3. 9.3.3  SerDes PLL
      4. 9.3.4  SerDes Equalizer
      5. 9.3.5  JESD204B Descrambler
      6. 9.3.6  JESD204B Frame Assembly
      7. 9.3.7  SYNC Interface
      8. 9.3.8  Single or Dual Link Configuration
      9. 9.3.9  Multi-Device Synchronization
      10. 9.3.10 SYSREF Capture Circuit
      11. 9.3.11 JESD204B Subclass 0 Support
      12. 9.3.12 SerDes Test Modes through Serial Programming
      13. 9.3.13 SerDes Test Modes through IEEE 1500 Programming
      14. 9.3.14 Error Counter
      15. 9.3.15 Eye Scan
      16. 9.3.16 JESD204B Pattern Test
      17. 9.3.17 Wideband DUC (wide-DUC)
      18. 9.3.18 Interpolation Block
        1. 9.3.18.1 Multi-DUC input
        2. 9.3.18.2 Interpolation Filters
        3. 9.3.18.3 JESD204B Modes, Interpolation and Clock phase Programming
        4. 9.3.18.4 Digital Quadrature Modulator
        5. 9.3.18.5 Low Power Coarse Resolution Mixing Modes
        6. 9.3.18.6 Inverse Sinc Filter
      19. 9.3.19 PA Protection Block
      20. 9.3.20 Gain Block
      21. 9.3.21 Output Summation
      22. 9.3.22 Output Delay
      23. 9.3.23 Polarity Inversion
      24. 9.3.24 Temperature Sensor
      25. 9.3.25 Alarm Monitoring
      26. 9.3.26 Differential Clock Inputs
      27. 9.3.27 CMOS Digital Inputs
      28. 9.3.28 DAC Fullscale Output Current
      29. 9.3.29 Current Steering DAC Architecture
      30. 9.3.30 DAC Transfer Function
    4. 9.4 Device Functional Modes
      1. 9.4.1 Clocking Modes
      2. 9.4.2 PLL Bypass Mode Programming
      3. 9.4.3 Internal PLL/VCO
      4. 9.4.4 CLKOUT
      5. 9.4.5 Serial Peripheral Interface (SPI)
        1. 9.4.5.1 NORMAL (RW)
        2. 9.4.5.2 WRITE_TO_CLEAR (W0C)
    5. 9.5 Register Maps
      1. 9.5.1  Chip Reset and Configuration Register (address = 0x00) [reset = 0x5803]
        1. Table 48. RESET_CONFIG Field Descriptions
      2. 9.5.2  IO Configuration Register (address = 0x01) [reset = 0x1800]
        1. Table 49. IO_CONFIG Field Descriptions
      3. 9.5.3  Lane Single Detect Alarm Mask Register (address = 0x02) [reset = 0xFFFF]
        1. Table 50. ALM_SD_MASK Field Descriptions
      4. 9.5.4  Clock Alarms Mask Register (address = 0x03) [reset = 0xFFFF
        1. Table 51. ALM_CLK_MASK Field Descriptions
      5. 9.5.5  SERDES Loss of Signal Detection Alarms Register (address = 0x04) [reset = 0x0000]
        1. Table 52. ALM_SD_DET Field Descriptions
      6. 9.5.6  SYSREF Alignment Circuit Alarms Register (address = 0x05) [reset = 0x0000]
        1. Table 53. ALM_SYSREF_DET Field Descriptions
      7. 9.5.7  Temperature Sensor and PLL Loop Voltage Register (address = 0x06) [reset = variable]
        1. Table 54. TEMP_PLLVOLT Field Descriptions
      8. 9.5.8  Page Set Register (address = 0x09) [reset = 0x0000]
        1. Table 55. PAGE_SET Field Descriptions
      9. 9.5.9  SYSREF Align to r1 and r3 Count Register (address = 0x78) [reset = 0x0000]
        1. Table 56. SYSREF_ALIGN_R Field Descriptions
      10. 9.5.10 SYSREF Phase Count 1 and 2 Register (address = 0x79) [reset = 0x0000]
        1. Table 57. SYSREF12_CNT Field Descriptions
      11. 9.5.11 SYSREF Phase Count 3 and 4 Register (address = 0x7A) [reset = 0x0000]
        1. Table 58. SYSREF34_CNT Field Descriptions
      12. 9.5.12 Vendor ID and Chip Version Register (address = 0x7F) [reset = 0x0008]]
        1. Table 59. VENDOR_VER Field Descriptions
      13. 9.5.13 Multi-DUC Configuration (PAP, Interpolation) Register (address = 0x0A) [reset = 0x02B0]
        1. Table 60. MULTIDUC_CFG1 Field Descriptions
      14. 9.5.14 Multi-DUC Configuration (Mixers) Register (address = 0x0C) [reset = 0x2402]
        1. Table 61. MULTIDUC_CFG2 Field Descriptions
      15. 9.5.15 JESD FIFO Control Register (address = 0x0D) [reset = 0x1300]
        1. Table 62. JESD_FIFO Field Descriptions
      16. 9.5.16 Alarm Mask 1 Register (address = 0x0E) [reset = 0x00FF]
        1. Table 63. ALM_MASK1 Field Descriptions
      17. 9.5.17 Alarm Mask 2 Register (address = 0x0F) [reset = 0xFFFF]
        1. Table 64. ALM_MASK2 Field Descriptions
      18. 9.5.18 Alarm Mask 3 Register (address = 0x10) [reset = 0xFFFF]
        1. Table 65. ALM_MASK3 Field Descriptions
      19. 9.5.19 Alarm Mask 4 Register (address = 0x11) [reset = 0xFFFF]
        1. Table 66. ALM_MASK4 Field Descriptions
      20. 9.5.20 JESD Lane Skew Register (address = 0x12) [reset = 0x0000]
        1. Table 67. JESD_LN_SKEW Field Descriptions
      21. 9.5.21 CMIX Configuration Register (address = 0x17) [reset = 0x0000]
        1. Table 68. CMIX Field Descriptions
      22. 9.5.22 Output Summation and Delay Register (address = 0x19) [reset = 0x0000]
        1. Table 69. OUTSUM Field Descriptions
      23. 9.5.23 NCO Phase Path AB Register (address = 0x1C) [reset = 0x0000]
        1. Table 70. PHASE_NCOAB Field Descriptions
      24. 9.5.24 NCO Phase Path CD Register (address = 0x1D) [reset = 0x0000]
        1. Table 71. PHASE_NCOCD Field Descriptions
      25. 9.5.25 NCO Frequency Path AB Register (address = 0x1E-0x20) [reset = 0x0000 0000 0000]
        1. Table 72. FREQ_NCOAB Field Descriptions
      26. 9.5.26 NCO Frequency Path CD Register (address = 0x21-0x23) [reset = 0x0000 0000 0000]
        1. Table 73. FREQ_NCOCD Field Descriptions
      27. 9.5.27 SYSREF Use for Clock Divider Register (address = 0x24) [reset = 0x0010]
        1. Table 74. SYSREF_CLKDIV Field Descriptions
      28. 9.5.28 Serdes Clock Control Register (address = 0x25) [reset = 0x7700]
        1. Table 75. SERDES_CLK Field Descriptions
      29. 9.5.29 Sync Source Control 1 Register (address = 0x27) [reset = 0x1144]
        1. Table 76. SYNCSEL1 Field Descriptions
      30. 9.5.30 Sync Source Control 2 Register (address = 0x28) [reset = 0x0000]
        1. Table 77. SYNCSEL2 Field Descriptions
      31. 9.5.31 PAP path AB Gain Attenuation Step Register (address = 0x29) [reset = 0x0000]
        1. Table 78. PAP_GAIN_AB Field Descriptions
      32. 9.5.32 PAP path AB Wait Time Register (address = 0x2A) [reset = 0x0000]
        1. Table 79. PAP_WAIT_AB Field Descriptions
      33. 9.5.33 PAP path CD Gain Attenuation Step Register (address = 0x2B) [reset = 0x0000]
        1. Table 80. PAP_GAIN_CD Field Descriptions
      34. 9.5.34 PAP Path CD Wait Time Register (address = 0x2C) [reset = 0x0000]
        1. Table 81. PAP_WAIT_CD Field Descriptions
      35. 9.5.35 PAP path AB Configuration Register (address = 0x2D) [reset = 0x0FFF]
        1. Table 82. PAP_CFG_AB Field Descriptions
      36. 9.5.36 PAP path CD Configuration Register (address = 0x2E) [reset = 0x0FFF]
        1. Table 83. PAP_CFG_CD Field Descriptions
      37. 9.5.37 DAC SPI Configuration Register (address = 0x2F) [reset = 0x0000]
        1. Table 84. SPIDAC_TEST1 Field Descriptions
      38. 9.5.38 DAC SPI Constant Register (address = 0x30) [reset = 0x0000]
        1. Table 85. SPIDAC_TEST2 Field Descriptions
      39. 9.5.39 Gain for path AB Register (address = 0x32) [reset = 0x0000]
        1. Table 86. GAINAB Field Descriptions
      40. 9.5.40 Gain for path CD Register (address = 0x33) [reset = 0x0000]
        1. Table 87. GAINCD Field Descriptions
      41. 9.5.41 JESD Error Counter Register (address = 0x41) [reset = 0x0000]
        1. Table 88. JESD_ERR_CNT Field Descriptions
      42. 9.5.42 JESD ID 1 Register (address = 0x46) [reset = 0x0044]
        1. Table 89. JESD_ID1 Field Descriptions
      43. 9.5.43 JESD ID 2 Register (address = 0x47) [reset = 0x190A]
        1. Table 90. JESD ID 2 Register (JESD_ID2)
      44. 9.5.44 JESD ID 3 and Subclass Register (address = 0x48) [reset = 0x31C3]
        1. Table 91. JESD_ID3 Field Descriptions
      45. 9.5.45 JESD Lane Enable Register (address = 0x4A) [reset = 0x0003]
        1. Table 92. JESD_LN_EN Field Descriptions
      46. 9.5.46 JESD RBD Buffer and Frame Octets Register (address = 0x4B) [reset = 0x1300]
        1. Table 93. JESD_RBD_F Field Descriptions
      47. 9.5.47 JESD K and L Parameters Register (address = 0x4C) [reset = 0x1303]
        1. Table 94. JESD_K_L Field Descriptions
      48. 9.5.48 JESD M and S Parameters Register (address = 0x4D) [reset = 0x0100]
        1. Table 95. JESD_M_S Field Descriptions
      49. 9.5.49 JESD N, HD and SCR Parameters Register (address = 0x4E) [reset = 0x0F4F]
        1. Table 96. JESD_N_HD_SCR Field Descriptions
      50. 9.5.50 JESD Character Match and Other Register (address = 0x4F) [reset = 0x1CC1]
        1. Table 97. JESD_MATCH Field Descriptions
      51. 9.5.51 JESD Link Configuration Data Register (address = 0x50) [reset = 0x0000]
        1. Table 98. JESD_Link_CFG Field Descriptions
      52. 9.5.52 JESD Sync Request Register (address = 0x51) [reset = 0x00FF]
        1. Table 99. JESD_SYNC_REQ Field Descriptions
      53. 9.5.53 JESD Error Output Register (address = 0x52) [reset = 0x00FF]
        1. Table 100. JESD_ERR_OUT Field Descriptions
      54. 9.5.54 JESD ILA Check 1 Register (address = 0x53) [reset = 0x0100]
        1. Table 101. JESD_ILA_CFG1 Field Descriptions
      55. 9.5.55 JESD ILA Check 2 Register (address = 0x54) [reset = 0x8E60]
        1. Table 102. JESD_ILA_CFG2 Field Descriptions
      56. 9.5.56 JESD SYSREF Mode Register (address = 0x5C) [reset = 0x0001]
        1. Table 103. JESD_SYSR_MODE Field Descriptions
      57. 9.5.57 JESD Crossbar Configuration 1 Register (address = 0x5F) [reset = 0x0123]
        1. Table 104. JESD_CROSSBAR1 Field Descriptions
      58. 9.5.58 JESD Crossbar Configuration 2 Register (address = 0x60) [reset = 0x4567]
        1. Table 105. JESD_CROSSBAR2 Field Descriptions
      59. 9.5.59 JESD Alarms for Lane 0 Register (address = 0x64) [reset = 0x0000]
        1. Table 106. JESD_ALM_L0 Field Descriptions
      60. 9.5.60 JESD Alarms for Lane 1 Register (address = 0x65 01100101) [reset = 0x0000]
        1. Table 107. JESD_ALM_L1 Field Descriptions
      61. 9.5.61 JESD Alarms for Lane 2 Register (address = 0x66) [reset = 0x0000]
        1. Table 108. JESD_ALM_L2 Field Descriptions
      62. 9.5.62 JESD Alarms for Lane 3 Register (address = 0x67) [reset = 0x0000]
        1. Table 109. JESD_ALM_L3 Field Descriptions
      63. 9.5.63 JESD Alarms for Lane 4 Register (address = 0x68) [reset = 0x0000]
        1. Table 110. JESD_ALM_L4 Field Descriptions
      64. 9.5.64 JESD Alarms for Lane 5 Register (address = 0x69) [reset = 0x0000]
        1. Table 111. JESD_ALM_L5 Field Descriptions
      65. 9.5.65 JESD Alarms for Lane 6 Register (address = 0x6A [reset = 0x0000]
        1. Table 112. JESD_ALM_L6 Field Descriptions
      66. 9.5.66 JESD Alarms for Lane 7 Register (address = 0x6B) [reset = 0x0000]
        1. Table 113. JESD Alarms for Lane 7 Register (JESD_ALM_L7)
      67. 9.5.67 SYSREF and PAP Alarms Register (address = 0x6C) [reset = 0x0000]
        1. Table 114. ALM_SYSREF_PAP Field Descriptions
      68. 9.5.68 Clock Divider Alarms 1 Register (address = 0x6D) [reset = 0x0000]
        1. Table 115. ALM_CLKDIV1 Field Descriptions
      69. 9.5.69 Clock Configuration Register (address = 0x0A) [reset = 0xF000]
        1. Table 116. CLK_CONFIG Field Descriptions
      70. 9.5.70 Sleep Configuration Register (address = 0x0B) [reset = 0x0022]
        1. Table 117. SLEEP_CONFIG Field Descriptions
      71. 9.5.71 Divided Output Clock Configuration Register (address = 0x0C) [reset = 0x8000]
        1. Table 118. CLK_OUT Field Descriptions
      72. 9.5.72 DAC Fullscale Current Register (address = 0x0D) [reset = 0xF000]
        1. Table 119. DACFS Field Descriptions
      73. 9.5.73 Internal SYSREF Generator Register (address = 0x10) [reset = 0x0000]
        1. Table 120. LCMGEN Field Descriptions
      74. 9.5.74 Counter for Internal SYSREF Generator Register (address = 0x11) [reset = 0x0000]
        1. Table 121. LCMGEN_DIV Field Descriptions
      75. 9.5.75 SPI SYSREF for Internal SYSREF Generator Register (address = 0x12) [reset = 0x0000]
        1. Table 122. LCMGEN_SPISYSREF Field Descriptions
      76. 9.5.76 Digital Test Signals Register (address = 0x1B) [reset = 0x0000]
        1. Table 123. DTEST Field Descriptions
      77. 9.5.77 Sleep Pin Control Register (address = 0x23) [reset = 0xFFFF]
        1. Table 124. SLEEP_CNTL Field Descriptions
      78. 9.5.78 SYSREF Capture Circuit Control Register (address = 0x24) [reset = 0x1000]
        1. Table 125. SYSR_CAPTURE Field Descriptions
      79. 9.5.79 Clock Input and PLL Configuration Register (address = 0x31) [reset = 0x0200]
        1. Table 126. Clock Input and PLL Configuration Register (CLK_PLL_CFG)
      80. 9.5.80 PLL Configuration 1 Register (address = 0x32) [reset = 0x0308]
        1. Table 127. CONFIG1 Field Descriptions
      81. 9.5.81 PLL Configuration 2 Register (address = 0x33) [reset = 0x4018]
        1. Table 128. PLL_CONFIG2 Field Descriptions
      82. 9.5.82 LVDS Output Configuration Register (address = 0x34) [reset = 0x0000]
        1. Table 129. LVDS_CONFIG Field Descriptions
      83. 9.5.83 Fuse Farm clock divider Register (address = 0x35) [reset = 0x0018]
        1. Table 130. PLL_FDIV Field Descriptions
      84. 9.5.84 Serdes Clock Configuration Register (address = 0x3B) [reset = 0x0002]
        1. Table 131. SRDS_CLK_CFG Field Descriptions
      85. 9.5.85 Serdes PLL Configuration Register (address = 0x3C) [reset = 0x8228]
        1. Table 132. SRDS_PLL_CFG Field Descriptions
      86. 9.5.86 Serdes Configuration 1 Register (address = 0x3D) [reset = 0x0x0088]
        1. Table 133. RDS_CFG1 Field Descriptions
      87. 9.5.87 Serdes Configuration 2 Register (address = 0x3E) [reset = 0x0x0909]
        1. Table 134. SRDS_CFG2 Field Descriptions
      88. 9.5.88 Serdes Polarity Control Register (address = 0x3F) [reset = 0x0000]
        1. Table 135. SRDS_POL Field Descriptions
      89. 9.5.89 JESD204B SYNCB OUTPUT Register (address = 0x76) [reset = 0x0000]
        1. Table 136. SYNCBOUT Field Descriptions
  10. 10Application and Implementation
    1. 10.1 Application Information
      1. 10.1.1 Start-up Sequence
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
      3. 10.2.3 Calculating the JESD204B SerDes rate
      4. 10.2.4 Calculating valid JESD204B SYSREF Frequency
      5. 10.2.5 Application Curves
  11. 11Power Supply Recommendations
    1. 11.1 Power Supply Sequencing
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  13. 13デバイスおよびドキュメントのサポート
    1. 13.1 関連リンク
    2. 13.2 ドキュメントの更新通知を受け取る方法
    3. 13.3 サポート・リソース
    4. 13.4 商標
    5. 13.5 静電気放電に関する注意事項
    6. 13.6 Glossary
  14. 14メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

7 Pin Configuration and Functions

AAV Package
144-Pin (FCBGA)
Top View

Pin Functions

PIN I/O DESCRIPTION
NO. NAME
C11, C12, D11, E11, F12, J12, K11, L11, M11, M12 AGND – Analog ground.
K8 ALARM O CMOS output for ALARM condition. Default polarity is active low, but can be changed to active high via RESET_CONFIG alm_out_pol control bit..
G3 AMUX0 O Analog test pin for SerDes, Lane 0 to Lane 3. Can be left floating.
F3 AMUX1 O Analog test pin for SerDes, Lane 4 to Lane 7. Can be left floating.
C8 ATEST O Analog test pin for DAC, references and PLL. Can be left floating.
A7 CLKTX+ O Divided output clock, internal 100 Ω differential termination, self-biased, positive terminal.
A6 CLKTX- O Divided output clock, internal 100 Ω differential termination, self-biased, negative terminal.
A10 DACCLK+ I Device clock, internal 100 Ω differential termination, self-biased, positive terminal.
A9 DACCLK- I Device clock, internal 100 Ω differential termination, self-biased, negative terminal.
A12 DACCLKSE I Single ended device clock optional input. Can be left floating if not used, internal 50 Ω termination.
A2, B2, C2, D2, D6, E2, E7, F2, F6, G2, G7, H6, J7, K2, L2, L3, L4, L5, M6 DGND - Digital ground.
C10 EXTIO I/O Requires a 0.1 μF decoupling capacitor to AGND.
K7 GPI0 - Factory use only. User should GND.
M7 GPI1 - Factory use only. User should GND.
L7 GPO0 O Used for CMOS SYNC0\ signal.
L6 GPO1 O Used for CMOS SYNC1\ signal.
D3 IFORCE O Test pin for on chip parametrics. Can be left floating.
C9 RBIAS O Full-scale output current bias. Change the full-scale output current through DACFS in register DACFS (8.5.72). Expected to be 3.6 kΩ to GND for 40 mA full scale output.
K9 RESET I Active low input for chip RESET, which resets all the programming registers to their default state. Internal pull-up.
J1 RX0+ I CML SerDes interface lane 0 input, positive
K1 RX0- I CML SerDes interface lane 0 input, negative
M1 RX1+ I CML SerDes interface lane 1 input, positive
L1 RX1- I CML SerDes interface lane 1 input, negative
M2 RX2+ I CML SerDes interface lane 2 input, positive
M3 RX2- I CML SerDes interface lane 2 input, negative
M5 RX3+ I CML SerDes interface lane 3 input, positive
M4 RX3- I CML SerDes interface lane 3 input, negative
H1 RX4+ I CML SerDes interface lane 4 input, positive
G1 RX4- I CML SerDes interface lane 4 input, negative
E1 RX5+ I CML SerDes interface lane 5 input, positive
F1 RX5- I CML SerDes interface lane 5 input, negative
D1 RX6+ I CML SerDes interface lane 6 input, positive
C1 RX6- I CML SerDes interface lane 6 input, negative
A1 RX7+ I CML SerDes interface lane 7 input, positive
B1 RX7- I CML SerDes interface lane 7 input, negative
L9 SCLK I Serial interface clock. Internal pull-down.
M8 SDEN I Active low serial data enable, always an input to the DAC38RFxx. Internal pull-up.
M10 SDIO I/O Serial interface data. Bi-directional in 3-pin mode (default) and uni-directional input 4-pin mode. Internal pull-down.
M9 SDO O Uni-directional serial interface data output in 4-pin mode. The SDO pin is tri-stated in 3-pin interface mode (default).
L8 SLEEP I Active high asynchronous hardware power-down input. Internal pull-down.
C4 SYNC0+ O Synchronization request to transmitter for JESD204B link 0, LVDS positive output.
C3 SYNC0- O Synchronization request to transmitter for JESD204B link 0, LVDS negative output.
C7 SYNC1+ O Synchronization request to transmitter for JESD204B link 1, LVDS positive output.
C6 SYNC1- O Synchronization request to transmitter for JESD204B link 1, LVDS negative output.
A3 SYSREF+ I LVPECL SYSREF positive input, internal 100 Ω differential termination, self biased. This positive/negative pair is captured with the rising edge of DACCLKP/N. It is used for multiple DAC synchronization.
A4 SYSREF- I LVPECL SYSREF negative input, self biased, internal 100 Ω differential termination. (See the SYSREF+ description)
K4 TCLK I JTAG test clock. Internal pull-down
H4 TDI I JTAG test data in. Internal pull-up
J4 TDO O JTAG test data out. Internal pull-up
K3 TESTMODE - This pin is used for factory testing.
Recommended to connect to ground for normal operation.
K5 TMS I JTAG test mode select. Internal pull-up
J5 TRST I JTAG test reset. Internal pull-up. Must be connected to ground if not used
K6 TXENABLE I Transmit enable active high input. Internal pull-down.
This pin is ORed with spi_txenable bit in JESD_FIFO register to enable analog output data transmission.
To enable analog output data transmission, pull CMOS TXENABLE pin to high.
To disable analog output, pull CMOS TXENABLE pin to low. The DAC output is forced to midscale.
F11, J11 VDDA1 I Analog 1 V supply voltage. Must be separated from VDDDIG1 supply for best performance.
G11, H11 VDDA18 I Analog 1.8 V supply voltage. (1.8 V)
D8, E8 VDDPLL1 I Analog 1 V supply for PLL.
B9, B10 VDDAPLL18 I PLL analog supply voltage. (1.8 V)
D9, E9 VDDAVCO18 I Analog supply voltage for VCO (1.8 V)
G9, H9 VDDCLK1 I Internal clock buffer supply voltage (1 V).
It is recommended to isolate this supply from VDDDIG1 and VDDA1.
G8, H8 VDDL1_1 I DAC core supply voltage. (1 V)
G10, H10 VDDL2_1 I DAC core supply voltage. (1 V)
A5, B5, C5, D5, D7, E3, E4, E5, E6, F4, F5, G4, G5 VDDDIG1 I Digital supply voltage. (1 V).
It is recommended to isolate this supply from VDDCLK1 and VDDA1.
F7, H7, G6, J6 VDDE1 I Digital Encoder supply voltage (1 V).
Must be separated from VDDDIG1 supply
H5 VDDIO18 I Supply voltage for all digital I/O and CMOS I/O. (1.8 V)
G12, H12 VDDOUT18 I DAC output supply. (1.8 V)
H2, J2 VDDR18 I Supply voltage for SerDes. (1.8 V)
B3, B4 VDDS18 I Supply voltage for LVDS SYNC0+/- and SYNC1+/- (1.8 V)
H3, J3 VDDT1 I Supply voltage for SerDes termination. (1 V)
B6 VDDTX1 I Supply voltage for divided clock output. (1 V)
B7 VDDTX18 I Supply voltage for divided clock output . (1.8 V)
D10, E10, K10, L10 VEE18N I Analog supply voltage. (-1.8 V)
L12 VOUT1+ O DAC channel 1 output.
K12 VOUT1- O DAC channel 1 complementary output.
D12 VOUT2+ O DAC channel 2 output.
E12 VOUT2- O DAC channel 2 complementary output.
D4 VSENSE O Test pin for on chip parametrics. Can be left floating.
A8, A11, B8, B11, B12, F8, F9, F10, J8, J9, J10 VSSCLK - Clock ground.