JAJSTV7 March 2024 DAC39RF10-SEP , DAC39RF10-SP , DAC39RFS10-SEP , DAC39RFS10-SP
PRODMIX
MIN | NOM | MAX | UNIT | |||
---|---|---|---|---|---|---|
INPUT CLOCK (CLK+, CLK-) | ||||||
fCLK | Input clock frequency | 800 | 10400 | MHz | ||
SYSREF (SYSREF+, SYSREF-) | ||||||
tSYSREF_LOW | SYSREF Low Timing | 5*tCLK + 1 ns | ||||
tSYSREF_HIGH | SYSREF High Timing | 5*tCLK + 1 ns | ||||
tINV(SYSREF) | Width of invalid SYSREF capture region of CLK± period, indicating setup or hold time violation, as measured by SYSREF_POS status register(1) |
13 | ps | |||
tINV(TEMP) | Drift of invalid SYSREF capture region over temperature, positive number indicates a shift toward MSB of SYSREF_POS register | –0.05 | ps/°C | |||
tINV(VA11) | Drift of invalid SYSREF capture region over VDDSYS18 supply voltage, positive number indicates a shift toward MSB of SYSREF_POS register | 0.19 | ps/mV | |||
tSTEP(SP) | Delay of SYSREF_POS LSB | SYSREF_ZOOM = 0 | 20 | ps | ||
SYSREF_ZOOM = 1 | 9 | |||||
DC(SYSREF) | SYSREF duty cycle (asserted) when using a periodic SYSREF signal | SYSREF duty cycle (asserted) when using a periodic SYSREF signal | 50% | 55% | ||
t(PH_SYS) | Minimum SYSREF± assertion duration after SYSREF± rising edge event | 8 | ns | |||
RESET | ||||||
tRESET | Minimum RESET pulse width | 100 | ns | |||
TXENABLE | ||||||
tTXENABLE_LOW | TXENABLE Low Time | 102 | clock cycles |