JAJSTV7
March 2024
DAC39RF10-SEP
,
DAC39RF10-SP
,
DAC39RFS10-SEP
,
DAC39RFS10-SP
PRODMIX
1
1
特長
2
アプリケーション
3
概要
4
Device Comparison
5
Pin Configuration and Functions
6
Specifications
6.1
Absolute Maximum Ratings
6.2
ESD Ratings
6.3
Recommended Operating Conditions
6.4
Thermal Information
6.5
Electrical Characteristics - DC Specifications
6.6
Electrical Characteristics - AC Specifications
6.7
Electrical Characteristics - Power Consumption
6.8
Timing Requirements
6.9
Switching Characteristics
6.10
SPI and FRI Timing Diagrams
6.11
Typical Characteristics: Bandwidth and DC Linearity
6.12
Typical Characteristics: Single Tone Spectra
6.13
Typical Characteristics: Dual Tone Spectra
6.14
Typical Characteristics: Noise Spectral Density
6.15
Typical Characteristics: Power Dissipation and Supply Currents
6.16
Typical Characteristics: Linearity Sweeps
6.17
Typical Characteristics: Modulated Waveforms
6.18
Typical Characteristics: Phase and Amplitude Noise
7
Detailed Description
7.1
Overview
7.2
Functional Block Diagrams
7.3
Feature Description
7.3.1
DAC Output Modes
7.3.1.1
NRZ Mode
7.3.1.2
RTZ Mode
7.3.1.3
RF Mode
7.3.1.4
DES Mode
7.3.2
DAC Core
7.3.2.1
DAC Output Structure
7.3.2.2
Full-Scale Current Adjustment
7.3.3
DEM and Dither
7.3.4
Offset Adjustment
7.3.5
Clocking Subsystem
7.3.5.1
SYSREF Frequency Requirements
7.3.5.2
SYSREF Position Detector and Sampling Position Selection (SYSREF Windowing)
7.3.6
Digital Signal Processing Blocks
7.3.6.1
Digital Upconverter (DUC)
7.3.6.1.1
Interpolation Filters
7.3.6.1.2
Numerically Controlled Oscillator (NCO)
7.3.6.1.2.1
Phase-Continuous NCO Update Mode
7.3.6.1.2.2
Phase-coherent NCO Update Mode
7.3.6.1.2.3
Phase-sync NCO Update Mode
7.3.6.1.2.4
NCO Synchronization
7.3.6.1.2.4.1
JESD204C LSB Synchonization
7.3.6.1.2.5
NCO Mode Programming
7.3.6.1.3
Mixer Scaling
7.3.6.2
Channel Bonder
7.3.6.3
DES Interpolator
7.3.7
JESD204C Interface
7.3.7.1
Deviation from JESD204C Standard
7.3.7.2
Transport Layer
7.3.7.3
Scrambler and Descrambler
7.3.7.4
Link Layer
7.3.7.5
Physical Layer
7.3.7.6
Serdes PLL Control
7.3.7.7
Serdes Crossbar
7.3.7.8
Multi-Device Synchronization and Deterministic Latency
7.3.7.8.1
Programming RBD
7.3.7.9
Operation in Subclass 0 Systems
7.3.7.10
Link Reset
7.3.8
Alarm Generation
7.4
Device Functional Modes
7.4.1
DUC and DDS Modes
7.4.2
JESD204C Interface Modes
7.4.2.1
JESD204C Interface Modes
7.4.2.2
JESD204C Format Diagrams
7.4.2.2.1
16-bit Formats
7.4.2.2.2
12-bit Formats
7.4.2.2.3
8-bit Formats
7.4.3
NCO Synchronization Latency
7.4.4
Data Path Latency
7.5
Programming
7.5.1
Using the Standard SPI Interface
7.5.1.1
SCS
7.5.1.2
SCLK
7.5.1.3
SDI
7.5.1.4
SDO
7.5.1.5
Serial Interface Protocol
7.5.1.6
Streaming Mode
7.5.2
Using the Fast Reconfiguration Interface
7.5.3
SPI Register Map
8
Application and Implementation
8.1
Application Information
8.1.1
Startup Procedure for DUC/Bypass Mode
8.1.2
Startup Procedure for DDS Mode
8.1.3
Understanding Dual Edge Sampling Modes
8.1.4
Eye Scan Procedure
8.1.5
Pre/Post Cursor Analysis Procedure
8.1.6
Sleep and Disable Modes
8.1.7
Radiation Environment Recommendations
8.1.7.1
SPI Programming
8.1.7.2
JESD204C Reliability
8.1.7.3
NCO Reliability
8.1.7.3.1
NCO Frequency and Phase Correction (Strategy #1)
8.1.7.3.2
NCO Frequency Correction (Strategy No. 2)
8.2
Typical Application
8.2.1
S-Band Radar Transmitter
8.2.2
Design Requirements
8.2.3
Detailed Design Procedure
8.2.4
Detailed Clocking Subsystem Design Procedure
8.2.4.1
Example 1: SWAP-C Optimized
8.2.4.2
Example 2: Improved Phase Noise LMX2820 with External VCO
8.2.4.3
Example 3: Discrete Analog PLL for Best DAC Performance
8.2.4.4
10GHz Clock Generation
8.2.5
Application Curves
8.3
Power Supply Recommendations
8.3.1
Power Up and Down Sequence
8.4
Layout
8.4.1
Layout Guidelines and Example
9
Device and Documentation Support
9.1
ドキュメントの更新通知を受け取る方法
9.2
サポート・リソース
9.3
商標
9.4
静電気放電に関する注意事項
9.5
用語集
10
Revision History
11
Mechanical, Packaging, and Orderable Information
パッケージ・オプション
メカニカル・データ(パッケージ|ピン)
ACL|256
MPBGAY8
サーマルパッド・メカニカル・データ
発注情報
jajstv7_oa
jajstv7_pm
7
Detailed Description