JAJSRY8A November   2023  – March 2024 DAC39RF12 , DAC39RFS12

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Device Comparison
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics - DC Specifications
    6. 6.6  Electrical Characteristics - AC Specifications
    7. 6.7  Electrical Characteristics - Power Consumption
    8. 6.8  Timing Requirements
    9. 6.9  Switching Characteristics
    10. 6.10 SPI and FRI Timing Diagrams
    11. 6.11 Typical Characteristics: Bandwidth and DC Linearity
    12. 6.12 Typical Characteristics: Single Tone Spectra
    13. 6.13 Typical Characteristics: Dual Tone Spectra
    14. 6.14 Typical Characteristics: Noise Spectral Density
    15. 6.15 Typical Characteristics: Linearity Sweeps
    16. 6.16 Typical Characteristics: Modulated Waveforms
    17. 6.17 Typical Characteristics: Phase and Amplitude Noise
    18. 6.18 Typical Characteristics: Power Dissipation and Supply Currents
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagrams
    3. 7.3 Feature Description
      1. 7.3.1 DAC Output Modes
        1. 7.3.1.1 NRZ Mode
        2. 7.3.1.2 RTZ Mode
        3. 7.3.1.3 RF Mode
        4. 7.3.1.4 DES Mode
      2. 7.3.2 DAC Core
        1. 7.3.2.1 DAC Output Structure
        2. 7.3.2.2 Full-Scale Current Adjustment
      3. 7.3.3 DEM and Dither
      4. 7.3.4 Offset Adjustment
      5. 7.3.5 Clocking Subsystem
        1. 7.3.5.1 SYSREF Frequency Requirements
        2. 7.3.5.2 SYSREF Position Detector and Sampling Position Selection (SYSREF Windowing)
      6. 7.3.6 Digital Signal Processing Blocks
        1. 7.3.6.1 Digital Upconverter (DUC)
          1. 7.3.6.1.1 Interpolation Filters
          2. 7.3.6.1.2 Numerically Controlled Oscillator (NCO)
            1. 7.3.6.1.2.1 Phase-Continuous NCO Update Mode
            2. 7.3.6.1.2.2 Phase-coherent NCO Update Mode
            3. 7.3.6.1.2.3 Phase-sync NCO Update Mode
            4. 7.3.6.1.2.4 NCO Synchronization
              1. 7.3.6.1.2.4.1 JESD204C LSB Synchonization
            5. 7.3.6.1.2.5 NCO Mode Programming
          3. 7.3.6.1.3 Mixer Scaling
        2. 7.3.6.2 Channel Bonder
        3. 7.3.6.3 DES Interpolator
      7. 7.3.7 JESD204C Interface
        1. 7.3.7.1  Deviation from JESD204C Standard
        2. 7.3.7.2  Transport Layer
        3. 7.3.7.3  Scrambler and Descrambler
        4. 7.3.7.4  Link Layer
        5. 7.3.7.5  Physical Layer
        6. 7.3.7.6  Serdes PLL Control
        7. 7.3.7.7  Serdes Crossbar
        8. 7.3.7.8  Multi-Device Synchronization and Deterministic Latency
          1. 7.3.7.8.1 Programming RBD
        9. 7.3.7.9  Operation in Subclass 0 Systems
        10. 7.3.7.10 Link Reset
      8. 7.3.8 Alarm Generation
    4. 7.4 Device Functional Modes
      1. 7.4.1 DUC and DDS Modes
      2. 7.4.2 JESD204C Interface Modes
        1. 7.4.2.1 JESD204C Interface Modes
        2. 7.4.2.2 JESD204C Format Diagrams
          1. 7.4.2.2.1 16-bit Formats
          2. 7.4.2.2.2 12-bit Formats
          3. 7.4.2.2.3 8-bit Formats
      3. 7.4.3 NCO Synchronization Latency
      4. 7.4.4 Data Path Latency
    5. 7.5 Programming
      1. 7.5.1 Using the Standard SPI Interface
        1. 7.5.1.1 SCS
        2. 7.5.1.2 SCLK
        3. 7.5.1.3 SDI
        4. 7.5.1.4 SDO
        5. 7.5.1.5 Serial Interface Protocol
        6. 7.5.1.6 Streaming Mode
      2. 7.5.2 Using the Fast Reconfiguration Interface
      3. 7.5.3 SPI Register Map
  9. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Startup Procedure for DUC/Bypass Mode
      2. 8.1.2 Startup Procedure for DDS Mode
      3. 8.1.3 Eye Scan Procedure
      4. 8.1.4 Pre/Post Cursor Analysis Procedure
      5. 8.1.5 Understanding Dual Edge Sampling Modes
      6. 8.1.6 Sleep and Disable Modes
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Transmitter Design Procedure
        1. 8.2.2.1 Detailed Clocking Subsystem Design Procedure
          1. 8.2.2.1.1 Example 1: SWAP-C Optimized
          2. 8.2.2.1.2 Example 2: Improved Phase Noise LMX2820 with External VCO
          3. 8.2.2.1.3 Example 3: Discrete Analog PLL for Best DAC Performance
          4. 8.2.2.1.4 12 GHz Clock Generation
      3. 8.2.3 Application Curves
    3. 8.3 Power Supply Recommendations
      1. 8.3.1 Power Up and Down Sequence
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines and Example
  10. 9 Device and Documentation Support
    1. 9.1 ドキュメントの更新通知を受け取る方法
    2. 9.2 サポート・リソース
    3. 9.3 商標
    4. 9.4 静電気放電に関する注意事項
    5. 9.5 用語集
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

6.9 Switching Characteristics

Typical values at TA = +25°C, minimum and maximum values over operating free-air temperature range, typical supply voltages, fCLK = 12 GHz, IFS_SWITCH = 20.5 mA, single tone amplitude = 0 dBFS, Dither and DEM enabled, unless otherwise noted.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
JESD204C SERDES INTERFACE [15:0]SRX-/+
fSERDES SERDES bit rate(4) .78125 12.8 Gbps
UI Unit Interval
78.125

 1280 ps
LATENCY
TDAC DAC clock period 1 / fCLK s
tPD(RX) Serdes RX analog propagation delay Serdes RX analog propagation delay 215 ps
tPDI Input clock rising edge cross-over to output sample cross-over Input clock rising edge cross-over to output sample cross-over 500 ps
tDACLAT Digital path latency from SYSREF rising edge to DAC output See XLS Calculator
tRELEASE Latency from SYSREF rising edge to elastic buffer release See XLS Calculator
tRXIN Latency from SERDES Input to elastic buffer release See XLS Calculator
tTXEN_OUTPUT TXENABLE rising edge to data output of DAC FAST_TX_EN = 0 varies(1) CLK Cycles
FAST_TX_EN=1 and QUIET_TX_DISABLE=0 93
FAST_TX_EN=1 and QUIET_TX_DISABLE=1 133
tTXEN_MUTE TXENABLE falling edge to DAC output muted QUIET_TX_DISABLE=0 93
QUIET_TX_DISABLE=1 133
tTXEN_PW Required TXENABLE pulse width FAST_TX_EN = 0(2) 102
FAST_TX_EN = 1(3) 20
SERIAL PROGRAMMING INTERFACE
Fs_c serial clock frequency 15.625 MHz
Fs_cts serial clock frequency temp sensor TS_TEMP register read 1 MHz
tP serial clock period 64 ns
tPH serial clock pulse width high 32 ns
tPL serial clock pulse width low 32 ns
tSU SDI setup time 30 ns
tH SDI hold time 3 ns
tIZ SDI TRI-STATE 3 ns
tODZ SDO driven to TRI-STATE 200 fF load 5 ns
tOZD SDO TRI-STATE to driven 200 fF load 3 ns
tOD SDO output delay 200 fF load 3 ns
tCSS SCS setup 30 ns
tCSH SCS hold 3 ns
tRS RESET setup to serial clock RESET high 30 ns
tRH RESET hold to serial clock RESET high 30 ns
tIAG Inter-access gap 30 ns
FAST RECONFIGURATION (FR) INTERFACE
FFRCLK FRCLK frequency 200 MHz
tFRCLK_P FRCLK period 5 ns
tFRCLK_PH FRCLK pulse width high 2 ns
t FRCLK_PL FRCLK pulse width low 2 ns
t FRDI_SU FRDI setup time 1 ns
tFRDI_H FRDI hold time 1 ns
t FRCS_SU FRCS setup time 1 ns
tFRCS_H FRCS hold time 1 ns
tFR_IAG Inter-access gap 1 ns
(1) The delay depends on how long it takes the JESD link to start up and the mode dependent device latency. Add the link layer startup time and the mode depedent latency (TDAC_LAT) from the latency calculator spreadsheet.
(2) Pulse durations less than this produce undefined behavior.
(3) Pulse durations less than this may have no effect on the output.
(4) 8b/10b encoding required for < 2 Gbps