JAJSML8 October 2020 DAC43401-Q1 , DAC53401-Q1
PRODUCTION DATA
The DACx3401-Q1 family of devices includes a power-on reset (POR) function that controls the output voltage at power up. After the VDD supply has been established, a POR event is issued. The POR causes all registers to initialize to default values, and communication with the device is valid only after a 30-ms, POR delay. The default value for all the registers in the DACx3401-Q1 is loaded from NVM as soon as the POR event is issued.
When the device powers up, a POR circuit sets the device to the default mode. The POR circuit requires specific VDD levels, as indicated in Figure 8-1, in order to make sure that the internal capacitors discharge and reset the device on power up. To make sure that a POR occurs, VDD must be less than 0.7 V for at least 1 ms. When VDD drops to less than 1.65 V, but remains greater than 0.7 V (shown as the undefined region), the device may or may not reset under all specified temperature and power-supply conditions. In this case, initiate a POR. When VDD remains greater than 1.65 V, a POR does not occur.