JAJSML8 October 2020 DAC43401-Q1 , DAC53401-Q1
PRODUCTION DATA
MIN | NOM | MAX | UNIT | ||
---|---|---|---|---|---|
fSCLK | SCL frequency | 1 | MHz | ||
tBUF | Bus free time between stop and start conditions | 0.5 | µs | ||
tHDSTA | Hold time after repeated start | 0.26 | µs | ||
tSUSTA | Repeated start setup time | 0.26 | µs | ||
tSUSTO | Stop condition setup time | 0.26 | µs | ||
tHDDAT | Data hold time | 0 | ns | ||
tSUDAT | Data setup time | 50 | ns | ||
tLOW | SCL clock low period | 0.5 | µs | ||
tHIGH | SCL clock high period | 0.26 | µs | ||
tF | Clock and data fall time | 120 | ns | ||
tR | Clock and data rise time | 120 | ns |