The TL431LI-Q1 adjustable, precision shunt regulator can be used to supply the DAC43901-Q1 from the 12-V system voltage. The TL431LI-Q1 has a 2.5-V precision reference. Two 10-kΩ resistors are used, as shown in the simplified figure, to regulate the output voltage to 5 V to supply DAC43901-Q1.

The state machine in DAC43901-Q1 is enabled by default; therefore, the PWM outputs are used with the preset parameters when the VREF/MODE pin is pulled high. To change these default parameters, pull the VREF/MODE pin low to enter programming mode, and write a 0 to the SM-START and SM-EN bits of the STATE-MACHINE-CONFIG0 register to disable the state machine. After the state machine is disabled, program the following SRAM parameters and register settings:

On the rising edge of TRIG-IN, the DAC43901-Q1 PWM outputs fade-in to the 7-bit PWM duty cycle defined in the PWM-MAX parameter located in bits [6:0] of SRAM location 0x21. On the falling edge of TRIG-IN, the PWM outputs fade-out to the 7-bit PWM duty cycle defined in the PWM-MIN parameter located in bits [6:0] of SRAM location 0x20.

The 5-bit PWM frequency is set in the PWM-FREQ parameter located in bits [11:7] of SRAM location 0x22. The available PWM frequencies are given in Table 7-7. The TPS92633-Q1 LED driver used in the example schematic recommends a 200-Hz PWM frequency with a 1% to 100% duty cycle for brightness control. In that case, the maximum frequency setting of 31 can be set in PWM-FREQ to get a PWM output frequency of 218 Hz. Make sure to left-shift this value by 7 bits when loading the parameter into the SRAM location.

Both PWM output channels use the same fade-in rate and fade-out rate as defined in the FADE-IN SLEW-RATE and FADE-OUT SLEW-RATE parameters located in bits [15:0] of SRAM locations 0x23 and 0x26, respectively. The total fade-in or fade-out time can be calculated using Equation 4 and Equation 5. The SLEW-RATE parameter is used in Equation 4 to get the t_{SLEW_RATE} in ms/step. For example, if a value of 2366 is used for the FADE-IN SLEW-RATE parameter, the resulting t_SLEW-RATE is 5.68 ms/step.

The information given in Table 7-5 is used to calculate the total number of duty-cycle steps in the fade-in or fade-out transition. If PWM-MIN is set to 0 and PWM-MAX is set to 0x7F, a total of 176 steps are needed. Equation 5 is used to calculate the total fade time, t_FADE as one second.

The delays between each channel are configured in the CH0-DELAY and COM-DELAY parameters in bits [15:0] of SRAM location 0x24 and 0x25, respectively. CH0-DELAY represents the delay between the rising edge of trigger and the start of channel 0. COM-DELAY represents the delay between the start of channel 0 and the start of channel 1. The delay time is calculated using Equation 7. If a delay value of 88 is set in the COM-DELAY parameter, the delay between the start of channel 0 and start of channel 1 is 500 ms.

After all register settings and SRAM parameters are configured, restart the state machine by writing ones to the SM-START and SM-EN bits of the STATE-MACHINE-CONFIG0 register. Save these settings to the NVM by writing a 1 to the NVM-PROG bit of the COMMON-TRIGGER register. Pull the VREF/MODE pin high to put DAC43901-Q1 in standalone mode and enable the PWM outputs on the digital interface pins.

The pseudocode for getting started with a logarithmic fade-in fade-out application is as follows:

//SYNTAX: WRITE <REGISTER NAME (REGISTER ADDRESS)>, <MSB DATA>, <LSB DATA>
//Pull VREF/MODE pin low to enter programming mode
//Disable the state machine
WRITE STATE-MACHINE-CONFIG0(0x27), 0x00, 0x00
//Power-up DAC channel 0, disable the internal reference
WRITE COMMON-CONFIG(0x1F), 0x03, 0xFF
//Enable comparator settings for channel 0, and set reference to VDD
WRITE DAC-0-VOUT-CMP-CONFIG(0x15), 0x04, 0x07
//Set the comparator threshold to mid-scale
WRITE SRAM-ADDR(0x2B), 0x00, 0x27
WRITE SRAM-DATA(0x2C), 0x80, 0x00
//Set max PWM duty cycle to 100%
WRITE SRAM-ADDR(0x2B), 0x00, 0x21
WRITE SRAM-DATA(0x2C), 0x00, 0x7F
//Set min PWM duty cycle to 0%
WRITE SRAM-ADDR(0x2B), 0x00, 0x20
WRITE SRAM-DATA(0x2C), 0x00, 0x00
//Set PWM frequency to 218Hz
WRITE SRAM-ADDR(0x2B), 0x00, 0x22
WRITE SRAM-DATA(0x2C), 0x0F, 0x80
//Set fade-in time to 1 s
WRITE SRAM-ADDR(0x2B), 0x00, 0x23
WRITE SRAM-DATA(0x2C), 0x09, 0x39
//Set fade-out time to 1 s
WRITE SRAM-ADDR(0x2B), 0x00, 0x26
WRITE SRAM-DATA(0x2C), 0x09, 0x3E
//Set the CH0 delay to 0
WRITE SRAM-ADDR(0x2B), 0x00, 0x24
WRITE SRAM-DATA(0x2C), 0x00, 0x00
//Set the COM delay to 500 ms
WRITE SRAM-ADDR(0x2B), 0x00, 0x25
WRITE SRAM-DATA(0x2C), 0x00, 0x58
//Enable and start the state machine
WRITE STATE-MACHINE-CONFIG0(0x27), 0x00, 0x03
//Save all settings in NVM
WRITE COMMON-TRIGGER(0x20) 0x00, 0x02
//Pull the VREF/MODE pin high to enter standalone mode