JAJSML8
October 2020
DAC43401-Q1
,
DAC53401-Q1
PRODUCTION DATA
1
特長
2
アプリケーション
3
概要
4
Revision History
5
Device Comparison Table
6
Pin Configuration and Functions
7
Specifications
7.1
Absolute Maximum Ratings
7.2
ESD Ratings
7.3
Recommended Operating Conditions
7.4
Thermal Information
7.5
Electrical Characteristics
7.6
Timing Requirements: I2C Standard Mode
7.7
Timing Requirements: I2C Fast Mode
7.8
Timing Requirements: I2C Fast Mode Plus
7.9
Typical Characteristics: VDD = 1.8 V (Reference = VDD) or VDD = 2 V (Internal Reference)
7.10
Typical Characteristics: VDD = 5.5 V (Reference = VDD) or VDD = 5 V (Internal Reference)
7.11
Typical Characteristics
8
Detailed Description
8.1
Overview
8.2
Functional Block Diagram
8.3
Feature Description
8.3.1
Digital-to-Analog Converter (DAC) Architecture
8.3.1.1
Reference Selection and DAC Transfer Function
8.3.1.1.1
Power Supply as Reference
8.3.1.1.2
Internal Reference
8.3.2
DAC Update
8.3.2.1
DAC Update Busy
8.3.3
Nonvolatile Memory (EEPROM or NVM)
8.3.3.1
NVM Cyclic Redundancy Check
8.3.3.2
NVM_CRC_ALARM_USER Bit
8.3.3.3
NVM_CRC_ALARM_INTERNAL Bit
8.3.4
Programmable Slew Rate
8.3.5
Power-on-Reset (POR)
8.3.6
Software Reset
8.3.7
Device Lock Feature
8.3.8
PMBus Compatibility
8.4
Device Functional Modes
8.4.1
Power Down Mode
8.4.2
Continuous Waveform Generation (CWG) Mode
8.4.3
PMBus Compatibility Mode
8.5
Programming
8.5.1
F/S Mode Protocol
8.5.2
I2C Update Sequence
8.5.2.1
Address Byte
8.5.2.2
Command Byte
8.5.3
I2C Read Sequence
8.6
Register Map
8.6.1
STATUS Register (address = D0h) [reset = 000Ch or 0014h]
8.6.2
GENERAL_CONFIG Register (address = D1h) [reset = 01F0h]
8.6.3
TRIGGER Register (address = D3h) [reset = 0008h]
8.6.4
DAC_DATA Register (address = 21h) [reset = 0000h]
8.6.5
DAC_MARGIN_HIGH Register (address = 25h) [reset = 0000h]
8.6.6
DAC_MARGIN_LOW Register (address = 26h) [reset = 0000h]
8.6.7
PMBUS_OPERATION Register (address = 01h) [reset = 0000h]
8.6.8
PMBUS_STATUS_BYTE Register (address = 78h) [reset = 0000h]
8.6.9
PMBUS_VERSION Register (address = 98h) [reset = 2200h]
9
Application and Implementation
9.1
Application Information
9.2
Typical Applications
9.2.1
Programmable LED Biasing
9.2.1.1
Design Requirements
9.2.1.2
Detailed Design Procedure
9.2.1.3
Application Curves
9.2.2
Power-Supply Margining
9.2.2.1
Design Requirements
9.2.2.2
Detailed Design Procedure
9.2.2.3
Application Curves
10
Power Supply Recommendations
11
Layout
11.1
Layout Guidelines
11.2
Layout Example
12
Device and Documentation Support
12.1
Documentation Support
12.1.1
Related Documentation
12.2
ドキュメントの更新通知を受け取る方法
12.3
サポート・リソース
12.4
Trademarks
12.5
静電気放電に関する注意事項
12.6
用語集
13
Mechanical, Packaging, and Orderable Information
パッケージ・オプション
メカニカル・データ(パッケージ|ピン)
DSG|8
MPDS308C
サーマルパッド・メカニカル・データ
DSG|8
QFND141I
発注情報
jajsml8_oa
jajsml8_pm
1
特長
車載アプリケーション用に AEC-Q100 認定取得済み:
温度グレード 1:–40℃~+125℃、T
A
1 LSB の INL と DNL (10 ビットおよび 8 ビット)
幅広い動作範囲:
電源:1.8V~5.5V
PMBus™
互換 I
2
C インターフェイス
Standard、Fast、Fast mode plus
A0 ピンによって 4 つのスレーブ・アドレス・オプションを設定
V
IH
:1.62V (V
DD
= 5.5V の場合)
ユーザーがプログラム可能な不揮発性メモリ (NVM、EEPROM)
すべてのレジスタ設定の保存と復元
プログラム可能な波形生成:方形波、ランプ波形、のこぎり波
三角波と FB ピンを使用する、パルス幅変調 (PWM) 出力
デジタル・スルーレート制御
内部基準電圧
非常に低い消費電力:1.8V で 0.2mA
柔軟な起動:ハイ・インピーダンスまたは 10K-GND
超小型パッケージ:8 ピン WSON (2mm × 2mm)