JAJSK36A October   2020  – September 2023 DAC43701-Q1 , DAC53701-Q1

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Revision History
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics
    6. 6.6  Timing Requirements: I2C Standard Mode
    7. 6.7  Timing Requirements: I2C Fast Mode
    8. 6.8  Timing Requirements: I2C Fast-Mode Plus
    9. 6.9  Timing Requirements: GPI
    10. 6.10 Timing Diagram
    11. 6.11 Typical Characteristics: VDD = 5.5 V (Reference = VDD) or VDD = 5 V (Internal Reference)
    12. 6.12 Typical Characteristics: VDD = 1.8 V (Reference = VDD) or VDD = 2 V (Internal Reference)
    13. 6.13 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Digital-to-Analog Converter (DAC) Architecture
        1. 7.3.1.1 Reference Selection and DAC Transfer Function
          1. 7.3.1.1.1 Power Supply as Reference
          2. 7.3.1.1.2 Internal Reference
      2. 7.3.2 General-Purpose Input (GPI)
      3. 7.3.3 DAC Update
        1. 7.3.3.1 DAC Update Busy
      4. 7.3.4 Nonvolatile Memory (EEPROM or NVM)
        1. 7.3.4.1 NVM Cyclic Redundancy Check
        2. 7.3.4.2 NVM_CRC_ALARM_USER Bit
        3. 7.3.4.3 NVM_CRC_ALARM_INTERNAL Bit
      5. 7.3.5 Programmable Slew Rate
      6. 7.3.6 Power-On Reset (POR)
      7. 7.3.7 Software Reset
      8. 7.3.8 Device Lock Feature
      9. 7.3.9 PMBus Compatibility
    4. 7.4 Device Functional Modes
      1. 7.4.1 Power Down Mode
      2. 7.4.2 Continuous Waveform Generation (CWG) Mode
      3. 7.4.3 PMBus Compatibility Mode
    5. 7.5 Programming
      1. 7.5.1 F/S Mode Protocol
      2. 7.5.2 I2C Update Sequence
        1. 7.5.2.1 Address Byte
          1. 7.5.2.1.1 Target Address Configuration
        2. 7.5.2.2 Command Byte
      3. 7.5.3 I2C Read Sequence
    6. 7.6 Register Map
      1. 7.6.1  STATUS Register (address = D0h) [reset = 000Ch or 0014h]
      2. 7.6.2  GENERAL_CONFIG Register (address = D1h) [reset = 01F0h]
      3. 7.6.3  CONFIG2 Register (address = D2h) [reset = device-specific]
      4. 7.6.4  TRIGGER Register (address = D3h) [reset = 0008h]
      5. 7.6.5  DAC_DATA Register (address = 21h) [reset = 0000h]
      6. 7.6.6  DAC_MARGIN_HIGH Register (address = 25h) [reset = device-specific]
      7. 7.6.7  DAC_MARGIN_LOW Register (address = 26h) [reset =device-specific]
      8. 7.6.8  PMBUS_OPERATION Register (address = 01h) [reset = 0000h]
      9. 7.6.9  PMBUS_STATUS_BYTE Register (address = 78h) [reset = 0000h]
      10. 7.6.10 PMBUS_VERSION Register (address = 98h) [reset = 2200h]
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 Power-Supply Margining
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
        3. 8.2.1.3 Application Curves
      2. 8.2.2 LED Thermal Foldback
        1. 8.2.2.1 Design Requirements
        2. 8.2.2.2 Detailed Design Procedure
        3. 8.2.2.3 Application Curves
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 ドキュメントの更新通知を受け取る方法
    3. 9.3 サポート・リソース
    4. 9.4 Trademarks
    5. 9.5 静電気放電に関する注意事項
    6. 9.6 用語集
  11. 10Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

8.2.1.2 Detailed Design Procedure

The DACx3701-Q1 features a Hi-Z power-down mode that is set by default at power up, unless the device is programmed otherwise using the NVM. When the DAC output is at Hi-Z, the current through R3 is zero and the SMPS is set at the nominal output voltage of 3.3 V. To have the same nominal condition when the DAC powers up, bring up the device at the same output as VFB (that is 0.6 V). This configuration makes sure there is no current through R3 even at power-up. Calculate R1 as (VOUT – VFB) / 100 µA = 27 kΩ.

To achieve ±10% margin-high and margin-low conditions, the DAC must sink or source additional current through R1. Calculate the current from the DAC (IMARGIN) using Equation 7 as 12 µA.

Equation 7. GUID-20201022-CA0I-XCTV-WQGC-1QPRNH9GBXNF-low.gif

where

  • IMARGIN is the margin current sourced or sunk from the DAC.
  • MARGIN is the percentage margin value divided by 100.
  • INOMINAL is the nominal current through R1 and R2.

To calculate the value of R3, first decide the DAC output range, and make sure to avoid the codes near zero-scale and full-scale for safe operation in the linear region. A DAC output of 20 mV is a safe consideration as the minimum output, and (1.8 V – 0.6 V – 20 mV = 1.18 V) as the maximum output. When the DAC output is at 20 mV, the power supply goes to margin high, and when the DAC output is at 1.18 V, the power supply goes to margin low. Calculate the value of R3 using Equation 8 as 48.3 kΩ. Choose a standard resistor value and adjust the DAC outputs. Choosing R3 = 47 kΩ makes the DAC margin high code as 1.164 V and the DAC margin low code as 36 mV.

Equation 8. GUID-20201022-CA0I-87FL-3X2Q-5N20HRNVRNNT-low.gif

The DACx3701-Q1 have a slew rate feature that is used to toggle between margin high, margin low, and nominal outputs with a defined slew rate. See the Table 7-17 for the slew rate setting details.

Note:

The MARGIN HIGH register value in DACx3701-Q1 results in the MARGIN LOW value at the power supply output. Similarly, the MARGIN LOW register value in DACx3701-Q1 results in the MARGIN HIGH value at the power-supply output.

The pseudocode for getting started with a power-supply control application is as follows:

//SYNTAX: WRITE <REGISTER NAME (Hex code)>, <MSB DATA>, <LSB DATA>
//Write DAC code (12-bit aligned) for nominal output
//For a 1.8-V output range, the 10-bit hex code for 0.6 V is 0x0155. 
//With 12-bit alignment, the hex code is 0x0554
WRITE DAC_DATA(0x21), 0x05, 0x54
//Write DAC code (12-bit aligned) for margin-low output at the power supply
//For a 1.8-V output range, the 10-bit hex code for 1.164 V is 0x0296. 
//With 12-bit alignment, the hex code is 0x0A58
WRITE DAC_MARGIN_HIGH(0x25), 0x0A, 0x58
//Write DAC code (12-bit aligned) for margin-high output at the power supply
//For a 1.8-V output range, the 10-bit hex code for 36 mV is 0x14. 
//With 12-bit alignment, the hex code is 0x50
WRITE DAC_MARGIN_LOW(0x26), 0x00, 0x50
//Power-up the device with enable internal reference with 1.5x output span. 
//This configuration outputs the nominal voltage (0.6 V)
//CODE_STEP: 2 LSB, SLEW_RATE: 25.6 µs
WRITE GENERAL_CONFIG(0xD1), 0x12, 0x14
//Trigger margin-low output at the power supply
WRITE TRIGGER(0xD3), 0x00, 0x80
//Trigger margin-high output at the power supply
WRITE TRIGGER(0xD3), 0x00, 0x40
//Write back DAC code (12-bit aligned) for nominal output
WRITE DAC_DATA(0x21), 0x05, 0x54