JAJSQO0 june   2023 DAC539E4W

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Revision History
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics: Threshold DAC
    6. 6.6  Electrical Characteristics: Comparator
    7. 6.7  Electrical Characteristics: General
    8. 6.8  Timing Requirements: I2C Standard Mode
    9. 6.9  Timing Requirements: I2C Fast Mode
    10. 6.10 Timing Requirements: I2C Fast Mode Plus
    11. 6.11 Timing Requirements: SPI Write Operation
    12. 6.12 Timing Requirements: SPI Read and Daisy Chain Operation (FSDO = 0)
    13. 6.13 Timing Requirements: SPI Read and Daisy Chain Operation (FSDO = 1)
    14. 6.14 Timing Diagrams
    15. 6.15 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Smart Digital-to-Analog Converter (DAC) Architecture
      2. 7.3.2 Threshold DAC
        1. 7.3.2.1 Voltage Reference and DAC Transfer Function
          1. 7.3.2.1.1 Power-Supply as Reference
          2. 7.3.2.1.2 Internal Reference
          3. 7.3.2.1.3 External Reference
      3. 7.3.3 Look-Up Table (LUT)
      4. 7.3.4 Programming Interface
      5. 7.3.5 Nonvolatile Memory (NVM)
        1. 7.3.5.1 NVM Cyclic Redundancy Check (CRC)
          1. 7.3.5.1.1 NVM-CRC-FAIL-USER Bit
          2. 7.3.5.1.2 NVM-CRC-FAIL-INT Bit
      6. 7.3.6 Power-On Reset (POR)
      7. 7.3.7 External Reset
      8. 7.3.8 Register-Map Lock
    4. 7.4 Device Functional Modes
      1. 7.4.1 Comparator Mode
        1. 7.4.1.1 Programmable Hysteresis Comparator
      2. 7.4.2 Power-Down Mode
    5. 7.5 Programming
      1. 7.5.1 SPI Programming Mode
      2. 7.5.2 I2C Programming Mode
        1. 7.5.2.1 F/S Mode Protocol
        2. 7.5.2.2 I2C Update Sequence
          1. 7.5.2.2.1 Address Byte
          2. 7.5.2.2.2 Command Byte
        3. 7.5.2.3 I2C Read Sequence
    6. 7.6 Register Maps
      1. 7.6.1  NOP Register (address = 00h) [reset = 0000h]
      2. 7.6.2  DAC-x-MARGIN-HIGH Register (address = 01h, 07h, 0Dh, 13h) [reset = 0000h]
      3. 7.6.3  DAC-x-MARGIN-LOW Register (address = 02h, 08h, 0Eh, 14h) [reset = 0000h]
      4. 7.6.4  DAC-x-VOUT-CMP-CONFIG Register (address = 03h, 09h, 0Fh, 15h) [reset = 0401h]
      5. 7.6.5  DAC-x-CMP-MODE-CONFIG Register (address = 05h, 0Bh, 11h, 17h) [reset = 0000h]
      6. 7.6.6  COMMON-CONFIG Register (address = 1Fh) [reset = 1249h]
      7. 7.6.7  COMMON-TRIGGER Register (address = 20h) [reset = 0000h]
      8. 7.6.8  COMMON-DAC-TRIG Register (address = 21h) [reset = 0000h]
      9. 7.6.9  GENERAL-STATUS Register (address = 22h) [reset = 00h, DEVICE-ID, VERSION-ID]
      10. 7.6.10 CMP-STATUS Register (address = 23h) [reset = 0000h]
      11. 7.6.11 DEVICE-MODE-CONFIG Register (address = 25h) [reset = 8040h]
      12. 7.6.12 INTERFACE-CONFIG Register (address = 26h) [reset = 0000h]
      13. 7.6.13 STATE-MACHINE-CONFIG0 Register (address = 27h) [reset = 0003h]
      14. 7.6.14 SRAM-CONFIG Register (address = 2Bh) [reset = 0000h]
      15. 7.6.15 SRAM-DATA Register (address = 2Ch) [reset = 0000h]
      16. 7.6.16 DAC-x-DATA Register (SRAM address = 21h, 22h, 23h, 24h) [reset = 8000h]
      17. 7.6.17 LUT-x-DATA Register (SRAM address = 25h through 34h) [reset = (see register description)]
      18. 7.6.18 LOOP-WAIT Register (SRAM address = 35h) [reset = 0000h]
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curve
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 ドキュメントの更新通知を受け取る方法
    2. 9.2 サポート・リソース
    3. 9.3 Trademarks
    4. 9.4 静電気放電に関する注意事項
    5. 9.5 用語集
  11. 10Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

8.2.2 Detailed Design Procedure

The GPO pins are open drain outputs. These pins must be pulled up to the desired IO voltage using external resistors.

This example connects the AINx and OUTx pins to simplify routing. The OUTx pins must be disabled as the comparator outputs by setting the CMP-x-OUT-EN bit to 0 in the DAC-x-VOUT-CMP-CONFIG register, which is the default setting.

Use Equation 5 to calculate the threshold codes stored in DAC-x-DATA.

Equation 5. THRESHOLD=VTHLD×2NVREF×GAIN

The DAC539E4W is a 10-bit device, which means the maximum DAC code is 1023d. For a 1-V VTHLD, DAC-0-DATA is calculated by Equation 6.

Equation 6. T H R E S H O L D = 1   V × 2 10 5   V = 204.8 d  

This result is rounded up to 205d (0x0CD). Table 8-2 lists the codes for the remaining threshold values.

Table 8-2 Threshold Codes
THRESHOLD VOLTAGEDAC-x-DATA[9:0]
1 V0x0CD
2 V0x19A
3 V0x266
4 V0x333

The AINx inputs are connected to the inverting input of the output buffer, and the threshold voltage is connected to the non-inverting input. By default, the comparator output is high when the voltage on AINx is lower than the threshold voltage. This example inverts the comparator outputs by setting the CMP-x-INV-EN bit in the DAC-x-VOUT-CMP-CONFIG register to 1.

By default the AINx inputs are high-impedance and the input voltage range is limited. This example sets the CMP-x-HIZ-IN-DIS bit in the DAC-x-VOUT-CMP-CONFIG register to 1 to connect the AINx inputs to a finite impedance. The input voltage range is 0 to VREF×Gain.

Table 8-36 shows the LUT configuration used in this example. This example application uses four different error codes, including 0b0000 representing no error. When the CMP0 and CMP1 outputs are high, the GPOs output 0b0011. When CMP2 is high, the GPOs output 0b0100. When all comparator outputs are high, the GPOs output 0b1111. All other conditions output 0b0000. Table 8-36 shows the LUT settings for this example.

Table 8-3 Comparator Input to GPO LUT
COMPARATOR OUTPUT STATUS
CMP3, CMP2, CMP1, CMP0		 OUTPUTS
GPO3, GPO2, GPO1, GPO0
0b0000 LUT-0-DATA: 0b0000
0b0001 LUT-1-DATA: 0b0000
0b0010 LUT-2-DATA: 0b0000
0b0011 LUT-3-DATA: 0b0011
0b0100 LUT-4-DATA: 0b0100
0b0101 LUT-5-DATA: 0b0100
0b0110 LUT-6-DATA: 0b0100
0b0111 LUT-7-DATA: 0b0100
0b1000 LUT-8-DATA: 0b0000
0b1001 LUT-9-DATA: 0b0000
0b1010 LUT-10-DATA: 0b0000
0b1011 LUT-11-DATA: 0b0000
0b1100 LUT-12-DATA: 0b0100
0b1101 LUT-13-DATA: 0b0100
0b1110 LUT-14-DATA: 0b0100
0b1111 LUT-15-DATA: 0b1111

The CMPx outputs are read and the GPOs updated in a continuous loop. A loop refresh delay can be used to decrease the frequency of the loop to avoid any switching noise on the outputs as the voltage on the AINx pins settle. The timer is 5 bits and is stored in the LOOP-WAIT SRAM register. Use Equation 4 to calculate the delay. Set the LOOP-REFRESH code to 19d for a 41-ms delay.

Follow these guidelines to set up the registers on the DAC539E4W:

  • Stop the state machine before updating the application parameters by writing 0 to the STATE-MACHINE-CONFIG0 register.
  • Set all of the application parameters shown in Table 8-4. These locations must be used to save the settings in the NVM.
  • LUT locations LUT-0-DATA, LUT-1-DATA, and LUT-15-DATA correspond to CMP3, CMP2, CMP1, and CMP0 equaling 0b0000, 0b0001, and 0b1111, respectively.
  • Configure the reference for all channels in the DAC-x-VOUT-CMP-CONFIG register. Configure each channel to operate in comparator mode by setting the CMP-x-EN bit to 1 in the same register.
  • Power on the comparator outputs using the COMMON-CONFIG register.
  • Set the DEVICE-MODE-CONFIG register to 0x8040.
  • Start the state machine by writing 0003h to the STATE-MACHINE-CONFIG0.
  • Trigger an NVM write by setting the NVM-PROG bit in the COMMON-TRIGGER register (0x20) to 1.

Table 8-4 Application Parameters
REGISTER NAMEADDRESS [BITS]ADDRESS LOCATION
DAC-0-DATA0x21[15:6]SRAM
DAC-1-DATA0x22[15:6]SRAM
DAC-2-DATA0x23[15:0]SRAM
DAC-3-DATA0x24[15:6]SRAM
LUT-0-DATA0x25[3:0]SRAM
LUT-1-DATA0x26[3:0]SRAM
LUT-2-DATA0x27[3:0]SRAM
LUT-3-DATA0x28[3:0]SRAM
LUT-4-DATA0x29[3:0]SRAM
LUT-5-DATA0x2A[3:0]SRAM
LUT-6-DATA0x2B[3:0]SRAM
LUT-7-DATA0x2C[3:0]SRAM
LUT-8-DATA0x2D[3:0]SRAM
LUT-9-DATA0x2E[3:0]SRAM
LUT-10-DATA0x2F[3:0]SRAM
LUT-11-DATA0x30[3:0]SRAM
LUT-12-DATA0x31[3:0]SRAM
LUT-13-DATA0x32[3:0]SRAM
LUT-14-DATA0x33[3:0]SRAM
LUT-15-DATA0x34[3:0]SRAM
LOOP-WAIT0x35[3:0]SRAM
DAC-0-VOUT-CMP-CONFIG0x03[12:10][4:0]Register
DAC-1-VOUT-CMP-CONFIG0x09[12:10][4:0]Register
DAC-2-VOUT-CMP-CONFIG0x0F[12:10][4:0]Register
DAC-3-VOUT-CMP-CONFIG0x15[12:10][4:0]Register
COMMON-CONFIG0x1F[15:0]Register
DEVICE-MODE-CONFIG0x25[15:0]Register
STATE-MACHINE-CONFIG00x27[2:0]Register

Only the bits listed in the address column of Table 8-4 are saved in NVM and used in the state machine. For example, only bits 12 to 10, and 4 to 0 are saved in NVM for the DAC-X-VOUT-CMP-CONFIG registers.

The pseudocode for this application example is as follows:

//SYNTAX: WRITE <REGISTER NAME (REGISTER ADDRESS)>, <MSB DATA>, <LSB DATA>
//Pull MODE pin low to enter programming mode//SYNTAX: WRITE <REGISTER NAME(Hex Code)>, <MSB DATA>, <LSB DATA>
//Stop the state machine
WRITE STATE-MACHINE-CONFIG(0x27), 0x00, 0x03
//Set the comparator thresholds
WRITE DAC-0-DATA(SRAM 0x21), 0x33, 0x40
WRITE DAC-1-DATA(SRAM 0x22), 0x66, 0x80
WRITE DAC-2-DATA(SRAM 0x23), 0x99, 0x80
WRITE DAC-3-DATA(SRAM 0x24), 0xCC, 0xC0
//Set the LUT values
WRITE LUT-0-DATA(SRAM 0x25), 0x00, 0x00
WRITE LUT-1-DATA(SRAM 0x26), 0x00, 0x00
WRITE LUT-2-DATA(SRAM 0x27), 0x00, 0x00
WRITE LUT-3-DATA(SRAM 0x28), 0x00, 0x03
WRITE LUT-4-DATA(SRAM 0x29), 0x00, 0x04
WRITE LUT-5-DATA(SRAM 0x2A), 0x00, 0x04
WRITE LUT-6-DATA(SRAM 0x2B), 0x00, 0x04
WRITE LUT-7-DATA(SRAM 0x2C), 0x00, 0x04
WRITE LUT-8-DATA(SRAM 0x2D), 0x00, 0x00
WRITE LUT-9-DATA(SRAM 0x2E), 0x00, 0x00
WRITE LUT-10-DATA(SRAM 0x2F), 0x00, 0x00
WRITE LUT-11-DATA(SRAM 0x30), 0x00, 0x03
WRITE LUT-12-DATA(SRAM 0x31), 0x00, 0x04
WRITE LUT-13-DATA(SRAM 0x32), 0x00, 0x04
WRITE LUT-14-DATA(SRAM 0x33), 0x00, 0x04
WRITE LUT-15-DATA(SRAM 0x34), 0x00, 0x0F
//Set the loop refresh setting for 41 ms
WRITE LOOP-WAIT(SRAM 0x35), 0x00, 0x13
//Set the channel 0 reference to VDD and enable comparator mode
WRITE DAC-0-VOUT-CMP-CONFIG(0x03), 0x04, 0x07
//Set channel 1 reference to VDD and enable comparator mode
WRITE DAC-1-VOUT-CMP-CONFIG(0x09), 0x04, 0x07
//Set channel 2 reference to VDD and enable comparator mode
WRITE DAC-2-VOUT-CMP-CONFIG(0x0F), 0x04, 0x07
//Set channel 3 reference to VDD and enable comparator mode
WRITE DAC-3-VOUT-CMP-CONFIG(0x15), 0x04, 0x07
//Power on the DAC channels
WRITE COMMON-CONFIG(0x1F), 0x02, 0x49
//Set the device mode (this is the device default)
WRITE DEVICE-MODE-CONFIG(0x25), 0x80, 0x40
//Start the state machine
WRITE STATE-MACHINE-CONFIG0(0x27), 0x00, 0x03
//Save settings to NVM
WRITE COMMON-TRIGGER(0x20), 0x00, 0x02
//Pull the MODE pin high to enter standalone mode