JAJSQO0 june 2023 DAC539E4W
PRODUCTION DATA
The DAC539E4W provides a user-programmable look-up table that maps the comparator inputs to the GPOs. This LUT can be stored in the NVM for standalone operation. Table 8-36 and Table 7-2 show the user-programmable LUT with different settings of the CMP-x-INV-EN bit in the DAC-x-VOUT-CMP-CONFIG register. Table 7-3 shows the pin mapping between the programming and standalone modes.
COMPARATOR INPUTS | USER-PROGRAMMABLE
OUTPUTS (DEFAULT VALUES) |
SRAM LOCATION | NAME | ||||||
---|---|---|---|---|---|---|---|---|---|
AIN3 | AIN2 | AIN1 | AIN0 | GPO3 | GPO2 | GPO1 | GPO0 | ||
0 | 0 | 0 | 0 | 1 | 1 | 1 | 1 | 0x25[3:0] | LUT-0-DATA |
0 | 0 | 0 | 1 | 1 | 1 | 1 | 0 | 0x26[3:0] | LUT-1-DATA |
0 | 0 | 1 | 0 | 1 | 1 | 0 | 1 | 0x27[3:0] | LUT-2-DATA |
0 | 0 | 1 | 1 | 1 | 1 | 0 | 0 | 0x28[3:0] | LUT-3-DATA |
0 | 1 | 0 | 0 | 1 | 0 | 1 | 1 | 0x29[3:0] | LUT-4-DATA |
0 | 1 | 0 | 1 | 1 | 0 | 1 | 0 | 0x2A[3:0] | LUT-5-DATA |
0 | 1 | 1 | 0 | 1 | 0 | 0 | 1 | 0x2B[3:0] | LUT-6-DATA |
0 | 1 | 1 | 1 | 1 | 0 | 0 | 0 | 0x2C[3:0] | LUT-7-DATA |
1 | 0 | 0 | 0 | 0 | 1 | 1 | 1 | 0x2D[3:0] | LUT-8-DATA |
1 | 0 | 0 | 1 | 0 | 1 | 1 | 0 | 0x2E[3:0] | LUT-9-DATA |
1 | 0 | 1 | 0 | 0 | 1 | 0 | 1 | 0x2F[3:0] | LUT-10-DATA |
1 | 0 | 1 | 1 | 0 | 1 | 0 | 0 | 0x30[3:0] | LUT-11-DATA |
1 | 1 | 0 | 0 | 0 | 0 | 1 | 1 | 0x31[3:0] | LUT-12-DATA |
1 | 1 | 0 | 1 | 0 | 0 | 1 | 0 | 0x32[3:0] | LUT-13-DATA |
1 | 1 | 1 | 0 | 0 | 0 | 0 | 1 | 0x33[3:0] | LUT-14-DATA |
1 | 1 | 1 | 1 | 0 | 0 | 0 | 0 | 0x34[3:0] | LUT-15-DATA |
COMPARATOR INPUTS | USER-PROGRAMMABLE
OUTPUTS (DEFAULT VALUES) |
SRAM LOCATION | NAME | ||||||
---|---|---|---|---|---|---|---|---|---|
AIN3 | AIN2 | AIN1 | AIN0 | GPO3 | GPO2 | GPO1 | GPO0 | ||
0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0x25[3:0] | LUT-0-DATA |
0 | 0 | 0 | 1 | 0 | 0 | 0 | 1 | 0x26[3:0] | LUT-1-DATA |
0 | 0 | 1 | 0 | 0 | 0 | 1 | 0 | 0x27[3:0] | LUT-2-DATA |
0 | 0 | 1 | 1 | 0 | 0 | 1 | 1 | 0x28[3:0] | LUT-3-DATA |
0 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 0x29[3:0] | LUT-4-DATA |
0 | 1 | 0 | 1 | 0 | 1 | 0 | 1 | 0x2A[3:0] | LUT-5-DATA |
0 | 1 | 1 | 0 | 0 | 1 | 1 | 0 | 0x2B[3:0] | LUT-6-DATA |
0 | 1 | 1 | 1 | 0 | 1 | 1 | 1 | 0x2C[3:0] | LUT-7-DATA |
1 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0x2D[3:0] | LUT-8-DATA |
1 | 0 | 0 | 1 | 1 | 0 | 0 | 1 | 0x2E[3:0] | LUT-9-DATA |
1 | 0 | 1 | 0 | 1 | 0 | 1 | 0 | 0x2F[3:0] | LUT-10-DATA |
1 | 0 | 1 | 1 | 1 | 0 | 1 | 1 | 0x30[3:0] | LUT-11-DATA |
1 | 1 | 0 | 0 | 1 | 1 | 0 | 0 | 0x31[3:0] | LUT-12-DATA |
1 | 1 | 0 | 1 | 1 | 1 | 0 | 1 | 0x32[3:0] | LUT-13-DATA |
1 | 1 | 1 | 0 | 1 | 1 | 1 | 0 | 0x33[3:0] | LUT-14-DATA |
1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0x34[3:0] | LUT-15-DATA |
STANDALONE MODE (MODE PIN IS HIGH) |
PROGRAMMING MODE (MODE PIN IS LOW) |
PIN NUMBER |
---|---|---|
GPO0 | SDA/SCLK | 8 |
GPO1 | A0/SDI | 7 |
GPO2 | SCL/SYNC | 6 |
GPO3 | NC/SDO | 5 |
The DAC539E4W provides a programmable delay between the comparator outputs and the GPOs to allow the analog inputs to settle the transitions. This delay is specified using the LOOP-REFRESH field in the LOOP-WAIT register. Equation 4 calculates the total delay in seconds using the decimal value of the LOOP-REFRESH field.