JAJSPS4A January   2023  – September 2023 DAC539G2-Q1

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Revision History
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics: Voltage Output
    6. 6.6  Electrical Characteristics: Comparator Mode
    7. 6.7  Electrical Characteristics: General
    8. 6.8  Timing Requirements: I2C Standard Mode
    9. 6.9  Timing Requirements: I2C Fast Mode
    10. 6.10 Timing Requirements: I2C Fast Mode Plus
    11. 6.11 Timing Requirements: SPI Write Operation
    12. 6.12 Timing Requirements: SPI Read and Daisy Chain Operation (FSDO = 0)
    13. 6.13 Timing Requirements: SPI Read and Daisy Chain Operation (FSDO = 1)
    14. 6.14 Timing Requirements: GPIO
    15. 6.15 Timing Diagrams
    16. 6.16 Typical Characteristics: Voltage Output
    17. 6.17 Typical Characteristics: Comparator
    18. 6.18 Typical Characteristics: General
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Smart Digital-to-Analog Converter (DAC) Architecture
      2. 7.3.2 Programming Interface
      3. 7.3.3 Nonvolatile Memory (NVM)
    4. 7.4 Device Functional Modes
      1. 7.4.1 GPI-to-Voltage Converter
        1. 7.4.1.1 Voltage Reference and DAC Transfer Function
        2. 7.4.1.2 Power-Supply as Reference
        3. 7.4.1.3 Internal Reference
        4. 7.4.1.4 External Reference
      2. 7.4.2 Voltage-to-PWM Converter
        1. 7.4.2.1 Function Generation
          1. 7.4.2.1.1 Triangular Waveform Generation
          2. 7.4.2.1.2 Sawtooth Waveform Generation
          3. 7.4.2.1.3 PWM Frequency Correction
      3. 7.4.3 Device Reset and Fault Management
        1. 7.4.3.1 Power-On Reset (POR)
        2. 7.4.3.2 External Reset
        3. 7.4.3.3 Register-Map Lock
        4. 7.4.3.4 NVM Cyclic Redundancy Check (CRC)
          1. 7.4.3.4.1 NVM-CRC-FAIL-USER Bit
          2. 7.4.3.4.2 NVM-CRC-FAIL-INT Bit
      4. 7.4.4 Power-Down Mode
    5. 7.5 Programming
      1. 7.5.1 SPI Programming Mode
      2. 7.5.2 I2C Programming Mode
        1. 7.5.2.1 F/S Mode Protocol
        2. 7.5.2.2 I2C Update Sequence
          1. 7.5.2.2.1 Address Byte
          2. 7.5.2.2.2 Command Byte
        3. 7.5.2.3 I2C Read Sequence
    6. 7.6 Register Maps
      1. 7.6.1  NOP Register (address = 00h) [reset = 0000h]
      2. 7.6.2  DAC-X-VOUT-CMP-CONFIG Register (address = 15h, 03h) [reset = 0400h]
      3. 7.6.3  COMMON-CONFIG Register (address = 1Fh) [reset = 03F9h]
      4. 7.6.4  COMMON-TRIGGER Register (address = 20h) [reset = 0000h]
      5. 7.6.5  FUNCTION-TRIGGER Register (address = 21h) [reset = 0001h]
      6. 7.6.6  GENERAL-STATUS Register (address = 22h) [reset = 2068h]
      7. 7.6.7  DEVICE-MODE-CONFIG Register (address = 25h) [reset = 8040h]
      8. 7.6.8  INTERFACE-CONFIG Register (address = 26h) [reset = 0000h]
      9. 7.6.9  STATE-MACHINE-CONFIG Register (address = 27h) [reset = 0003h]
      10. 7.6.10 SRAM-CONFIG Register (address = 2Bh) [reset = 0000h]
      11. 7.6.11 SRAM-DATA Register (address = 2Ch) [reset = 0000h]
      12. 7.6.12 FUNCTION-CONFIG Register (SRAM address = 20h) [reset = 007Ah]
      13. 7.6.13 FUNCTION-MAX Register (SRAM address = 21h) [reset = B900h]
      14. 7.6.14 FUNCTION-MIN Register (SRAM address = 22h) [reset = 1900h]
      15. 7.6.15 GPI-DEBOUNCE Register (SRAM address = 23h) [reset = 0138h]
      16. 7.6.16 VOUT-DATA-X Register (SRAM address = 24h to 2Bh) [reset = see #GUID-D64978E3-E8F0-4408-A2C1-8C72D24777EC/X6961 ]
      17. 7.6.17 PWM-FREQUENCY-ERROR Register (SRAM address = 9Eh) [reset = device-specific]
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Documentation Support
    2. 9.2 ドキュメントの更新通知を受け取る方法
    3. 9.3 サポート・リソース
    4. 9.4 Trademarks
    5. 9.5 静電気放電に関する注意事項
    6. 9.6 用語集
  11. 10Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

6.12 Timing Requirements: SPI Read and Daisy Chain Operation (FSDO = 0)

all input signals are specified with tr = tf = 1 V/ns (10% to 90% of VIO) and timed from a voltage level of (VIL + VIH) / 2,
1.7 V ≤ VIO ≤ 5.5 V, 1.7 V ≤ VDD ≤ 5.5 V,  –40°C ≤ TA ≤ +125°C, and FSDO = 0
MIN NOM MAX UNIT
fSCLK Serial clock frequency 1.25 MHz
tSCLKHIGH SCLK high time 350 ns
tSCLKLOW SCLK low time 350 ns
tSDIS SDI setup time 8 ns
tSDIH SDI hold time 8 ns
tCSS SYNC to SCLK falling edge setup time 400 ns
tCSH SCLK falling edge to SYNC rising edge 400 ns
tCSHIGH SYNC high time 1 µs
tSDODLY SCLK rising edge to SDO falling edge, IOL ≤ 5 mA, CL = 20 pF. 300 ns