JAJSPS4A January 2023 – September 2023 DAC539G2-Q1
PRODUCTION DATA
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
STATIC PERFORMANCE | ||||||
Offset error(1) (2) | 1.7 V ≤ VDD ≤ 5.5 V; DAC at midscale, comparator input at Hi-Z, and DAC operating with external reference | –7.5 | 0 | 7.5 | mV | |
Offset error time drift(1) | VDD = 5.5 V, TA = 125°C, FB in Hi-Z mode, DAC at full scale and VFB at 0 V or DAC at zero scale and VFB at 1.84 V, drift specified for 10 years of continuous operation | 4 | mV | |||
OUTPUT | ||||||
Input voltage | VREF connected to VDD, VFB resistor network connected to ground | 0 | VDD | V | ||
VREF connected to VDD, VFB resistor network disconnected from ground | 0 | VDD (1/3 – 1/100) | ||||
VOL | Logic low output voltage | ILOAD = 100 μA, output in open-drain mode | 0.1 | V | ||
DYNAMIC PERFORMANCE | ||||||
tresp | Output response time | DAC at midscale with 10-bit resolution, FB input at Hi-Z, and transition step at FB node is (VDAC – 2 LSB) to (VDAC + 2 LSB), transition time measured between 10% and 90% of output, output current of 100 µA, comparator output configured in push-pull mode, load capacitor at DAC output is 25 pF | 10 | µs |