JAJSED2B August 2017 – January 2018 DAC5672A
PRODUCTION DATA.
The data input ports of the DAC5672A accept a standard positive coding with data bits DA13 and DB13 being the most significant bits (MSB). The converter outputs support a clock rate of up to 275 MSPS. The best performance is typically achieved with a symmetric duty cycle for write and clock; however, the duty cycle may vary as long as the timing specifications are met. Similarly, the setup and hold times may be chosen within their specified limits.
All digital inputs of the DAC5672A are CMOS compatible. Figure 23 and Figure 24 show schematics of the equivalent CMOS digital inputs of the DAC5672A. The pullup and pulldown circuitry is approximately equivalent to 100 kΩ. The 14-bit digital data input follows the offset positive binary coding scheme. The DAC5672A is designed to operate with a digital supply (DVDD) of 3 V to 3.6 V.