JAJSGJ3E November   2018  – August 2023 DAC60501 , DAC70501 , DAC80501

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Revision History
  6. 5 Device Comparison Table
  7. 6 Pin Configuration and Functions
  8. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Electrical Characteristics
    6. 7.6  Timing Requirements: SPI Mode
    7. 7.7  Timing Requirements: I2C Standard Mode
    8. 7.8  Timing Requirements: I2C Fast Mode
    9. 7.9  Timing Requirements: I2C Fast-Mode Plus
    10. 7.10 Timing Diagrams
    11. 7.11 Typical Characteristics
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 DAC Architecture
        1. 8.3.1.1 DAC Transfer Function
        2. 8.3.1.2 DAC Register Structure
        3. 8.3.1.3 Output Amplifier
      2. 8.3.2 Internal Reference
        1. 8.3.2.1 Solder Heat Reflow
      3. 8.3.3 Power-On-Reset (POR)
      4. 8.3.4 Software Reset
    4. 8.4 Device Functional Modes
      1. 8.4.1 Power-Down Mode
    5. 8.5 Programming
      1. 8.5.1 Serial Interface
        1. 8.5.1.1 SPI Mode
          1. 8.5.1.1.1 SYNC Interrupt
        2. 8.5.1.2 I2C Mode
          1. 8.5.1.2.1 F/S Mode Protocol
          2. 8.5.1.2.2 I2C Update Sequence
            1. 8.5.1.2.2.1 Address Byte
            2. 8.5.1.2.2.2 Command Byte
            3. 8.5.1.2.2.3 Data Byte (MSDB and LSDB)
          3. 8.5.1.2.3 I2C Read Sequence
    6. 8.6 Register Map
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Charge Injection
        2. 9.2.2.2 Voltage Droop
        3. 9.2.2.3 Output Offset Error
        4. 9.2.2.4 Switch Selection
        5. 9.2.2.5 Amplifier Selection
        6. 9.2.2.6 Hold Capacitor Selection
      3. 9.2.3 Application Curves
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 ドキュメントの更新通知を受け取る方法
    3. 10.3 サポート・リソース
    4. 10.4 Trademarks
    5. 10.5 静電気放電に関する注意事項
    6. 10.6 用語集
  12. 11Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

8.6 Register Map

Table 8-7 Register Map
OFFSET REGISTER NAME REGISTER DESCRIPTION SECTION
0h NOOP No operation NOOP Register
1h DEVID Device identification DEVID Register
2h SYNC Synchronization SYNC Register
3h CONFIG Configuration CONFIG Register
4h GAIN Gain GAIN Register
5h TRIGGER Trigger TRIGGER Register
7h STATUS Status STATUS Register
8h DAC Digital-to-analog converter DAC Register

NOOP Register (offset = 0h) [reset = 0000h]

Figure 8-8 NOOP Register
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NOOP
W-0h
Table 8-8 NOOP Register Field Descriptions
Bit Field Type Reset Description
15-0 No operation W 0h No Operation command

DEVID Register (offset = 1h) [reset = 0115h for DAC80501Z, reset = 1115h for DAC70501Z, reset = 2115h for DAC60501Z, reset = 0195h for DAC80501M, reset = 1195h for DAC70501M, or reset = 2195h for DAC60501M]

Figure 8-9 DEVID Register
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 RESOLUTION 0 0 0 1 RSTSEL 0 0 1 0 1 0 1
R-0h R-000b (DAC80501) or 001b (DAC70501) or 010b (DAC60501) R-0h R-0h R-0h R-1h R-0h (DACx0501Z) or 1h (DACx0501M) R-0h R-0h R-1h R-0h R-1h R-0h R-1h
Table 8-9 DEVID Register Field Descriptions
Bit Field Type Reset Description
15 RESERVED R 0h RESERVED
14-12 RESOLUTION R 000b for DAC80501

DAC Resolution:

000b (DAC80501 16-bit)

001b (DAC70501 14-bit)

010b (DAC60501 12-bit)
001b for DAC70501
010b for DAC60501
11-8 RESERVED R 1h RESERVED
7 RSTSEL R 0h for DACx0501Z

DAC Power on Reset:

0h (DACx0501Z reset to zero scale)

1h (DACx0501M reset to midscale)
1h for DACx0501M
6-0 RESERVED R 15h RESERVED

SYNC Register (offset = 2h) [reset = 0000h]

Figure 8-10 SYNC Register
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED DAC_SYNC_EN
R/W-0h R/W-0h
Table 8-10 SYNC Register Field Descriptions
Bit Field Type Reset Description
15-1 RESERVED RW 0h RESERVED
0 DAC_SYNC_EN RW 0h When set to 1, the DAC output is set to update in response to an LDAC trigger (synchronous mode).
When cleared to 0 ,the DAC output is set to update immediately (asynchronous mode), default.

CONFIG Register (offset = 3h) [reset = 0000h]

Figure 8-11 CONFIG Register
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED REF_PWDWN RESERVED DAC_PWDWN
R/W-0h R/W-0h R/W-0h R/W-0h
Table 8-11 CONFIG Register Field Descriptions
Bit Field Type Reset Description
15-9 RESERVED RW 0h RESERVED
8 REF_PWDWN RW 0h When set to 1, this bit disables the device internal reference.
7-1 RESERVED RW 0h RESERVED
0 DAC_PWDWN RW 0h When set to 1, the DAC in power-down mode and the DAC output is connected to GND through a 1-kΩ internal resistor.

GAIN Register (offset = 4h) [reset = 0001h]

Figure 8-12 GAIN Register
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED REF-DIV RESERVED BUFF-GAIN
R/W-0h R/W-0h R/W-0h R/W-1h
Table 8-12 GAIN Register Field Descriptions
Bit Field Type Reset Description
15-9 RESERVED RW 0h RESERVED
8 REF-DIV RW 0h The reference voltage to the device (either from the internal or external reference) can be divided by a factor of two by setting the REF-DIV bit to 1. Make sure to configure REF-DIV so that there is sufficient headroom from VDD to the DAC operating reference voltage. Improper configuration of the reference divider triggers a reference alarm condition. In the case of an alarm condition, the reference buffer is shut down, and all the DAC outputs go to 0 V. The DAC data registers are unaffected by the alarm condition, and thus enable the DAC output to return to normal operation after the reference divider is configured correctly.
When REF-DIV set to 1, the reference voltage is internally divided by a factor of 2.
When REF-DIV is cleared to 0, the reference voltage is unaffected.
7-1 RESERVED RW 0h RESERVED
0 BUFF-GAIN RW 1h When set to 1, the buffer amplifier for corresponding DAC has a gain of 2.
When cleared to 0, the buffer amplifier for corresponding DAC has a gain of 1.

TRIGGER Register (offset = 5h) [reset = 0000h]

Figure 8-13 TRIGGER Register
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED LDAC SOFT-RESET [3:0]
R/W-0h W-0h W-0h
Table 8-13 TRIGGER Register Field Descriptions
Bit Field Type Reset Description
15-5 RESERVED RW 0h RESERVED
4 LDAC W 0h Set this bit to 1 to synchronously load the DAC in synchronous mode, This bit is self resetting.
3-0 SOFT-RESET [3:0] W 0h When set to the reserved code of 1010, this bit resets the device to the default state. These bits are self resetting.

STATUS Register (offset = 7h) [reset = 0000h]

Figure 8-14 STATUS Register
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED REF-ALARM
R/W-0h R-0h
Table 8-14 STATUS Register Field Descriptions
Bit Field Type Reset Description
15-1 RESERVED RW 0h RESERVED
0 REF-ALARM R 0 REF-ALARM bit. Reads 1 when the difference between the reference and supply pins is below a minimum analog threshold. Reads 0 otherwise. When 1, the reference buffer is shut down, and the DAC outputs are all zero volts. The DAC codes are unaffected, and the DAC output returns to normal when the difference is above the analog threshold.

DAC Register (offset = 8h) [reset = 0000h for DACx0501Z or reset = 8000h for DACx0501M]

Figure 8-15 DAC Register
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DAC-DATA [15:0]
R/W-0000h (DACx0501Z) or 8000h (DACx0501M)
Table 8-15 DAC Register Field Descriptions
Bit Field Type Reset Description
15-0 DAC-DATA [15:0] RW 0000h for DACx0501Z DAC data register.
Data are MSB aligned in straight binary format, and use the following format:

DAC80501: DATA[15:0]

DAC70501: DATA[13:0], 0, 0

DAC60501: DATA[11:0], 0, 0, 0, 0
8000h for DACx0501M