JAJSGJ3E November   2018  – August 2023 DAC60501 , DAC70501 , DAC80501

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Revision History
  6. 5 Device Comparison Table
  7. 6 Pin Configuration and Functions
  8. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Electrical Characteristics
    6. 7.6  Timing Requirements: SPI Mode
    7. 7.7  Timing Requirements: I2C Standard Mode
    8. 7.8  Timing Requirements: I2C Fast Mode
    9. 7.9  Timing Requirements: I2C Fast-Mode Plus
    10. 7.10 Timing Diagrams
    11. 7.11 Typical Characteristics
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 DAC Architecture
        1. 8.3.1.1 DAC Transfer Function
        2. 8.3.1.2 DAC Register Structure
        3. 8.3.1.3 Output Amplifier
      2. 8.3.2 Internal Reference
        1. 8.3.2.1 Solder Heat Reflow
      3. 8.3.3 Power-On-Reset (POR)
      4. 8.3.4 Software Reset
    4. 8.4 Device Functional Modes
      1. 8.4.1 Power-Down Mode
    5. 8.5 Programming
      1. 8.5.1 Serial Interface
        1. 8.5.1.1 SPI Mode
          1. 8.5.1.1.1 SYNC Interrupt
        2. 8.5.1.2 I2C Mode
          1. 8.5.1.2.1 F/S Mode Protocol
          2. 8.5.1.2.2 I2C Update Sequence
            1. 8.5.1.2.2.1 Address Byte
            2. 8.5.1.2.2.2 Command Byte
            3. 8.5.1.2.2.3 Data Byte (MSDB and LSDB)
          3. 8.5.1.2.3 I2C Read Sequence
    6. 8.6 Register Map
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Charge Injection
        2. 9.2.2.2 Voltage Droop
        3. 9.2.2.3 Output Offset Error
        4. 9.2.2.4 Switch Selection
        5. 9.2.2.5 Amplifier Selection
        6. 9.2.2.6 Hold Capacitor Selection
      3. 9.2.3 Application Curves
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 ドキュメントの更新通知を受け取る方法
    3. 10.3 サポート・リソース
    4. 10.4 Trademarks
    5. 10.5 静電気放電に関する注意事項
    6. 10.6 用語集
  12. 11Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

6 Pin Configuration and Functions

GUID-86131699-5D90-42D3-9D04-C3F2918F184D-low.svgFigure 6-1 DGS Package, 10-Pin VSSOP (Top View)
GUID-CC70CDD7-0832-4B83-94D6-C34445C17A76-low.svgFigure 6-2 DQF Package, 8-Pin WSON (Top View)
Table 6-1 Pin Functions
PIN TYPE DESCRIPTION
NAME DGS (VSSOP) DQF (WSON)
AGND 4 3 Ground Ground reference point for all circuitry on the device.
NC 3 — — No connection. Leave floating.
NC 9 — — No connection. Leave floating.
SCLK/SCL 6 5 Input Serial interface clock. SPI or I2C mode.
SDIN/SDA 8 7 Input/output SPI mode: Serial interface data input. Data are clocked into the input shift register on each falling edge of the SCLK pin.
I2C mode: Data are clocked into or out of the input register. This pin is a bidirectional, SDA drain data line that must be connected to the supply voltage with an external pullup resistor.
SPI2C 5 4 Input Interface select pin.
Digital interface in SPI mode if SPI2C = 0
Digital interface in I2C mode if SPI2C = 1
SPI2C pin must be kept static after device powers up.
SYNC/A0 7 6 Input SPI mode: Active low serial data enable. This input is the frame synchronization signal for the serial data. When the signal goes low, the serial interface input shift register is enabled.
I2C mode: Four-state address input 0.
VDD 1 1 Power Analog supply voltage (2.7 V to 5.5 V)
VOUT 2 2 Output Analog output voltage from the DAC
VREFIO 10 8 Input/output When using the internal reference, this pin is the reference output voltage pin (default). Reference input to the device when operating with external reference.