JAJSE78C August   2017  – January 2019 DAC60504 , DAC70504 , DAC80504

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     Device Images
      1.      ブロック概略図
  4. 4 改訂履歴
  5. 5 概要（続き）
  6. 6 Device Comparison Table
  7. 7 Pin Configuration and Functions
    1.     Pin Functions
  8. 8 Specifications
    1. 8.1 Absolute Maximum Ratings
    2. 8.2 ESD Ratings
    3. 8.3 Recommended Operating Conditions
    4. 8.4 Thermal Information
    5. 8.5 Electrical Characteristics
    6. 8.6 Typical Characteristics
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 Digital-to-Analog Converter (DAC)
        1. 9.3.1.1 DAC Transfer Function
        2. 9.3.1.2 Output Amplifiers
        3. 9.3.1.3 DAC Register Structure
          1. 9.3.1.3.1 DAC Register Synchronous and Asynchronous Updates
          2. 9.3.1.3.2 Broadcast DAC Register
      2. 9.3.2 Internal Reference
        1. 9.3.2.1 Reference Divider
        2. 9.3.2.2 Solder Heat Reflow
      3. 9.3.3 Device Reset Options
        1. 9.3.3.1 Power-on-Reset (POR)
        2. 9.3.3.2 Software Reset
    4. 9.4 Device Functional Modes
      1. 9.4.1 Stand-Alone Operation
      2. 9.4.2 Daisy-Chain Operation
      3. 9.4.3 Frame Error Checking
      4. 9.4.4 Power-Down Mode
    5. 9.5 Programming
    6. 9.6 Register Map
      1. 9.6.1 NOP Register (address = 0x00) [reset = 0x0000]
        1. Table 9. NOP Register Field Descriptions
      2. 9.6.2 DEVICE ID Register (address = 0x01) [reset = 0x---]
        1. Table 10. DEVICE ID Field Descriptions
      3. 9.6.3 SYNC Register (address = 0x2) [reset = 0xFF00]
        1. Table 11. SYNC Register Field Descriptions
      4. 9.6.4 CONFIG Register (address = 0x3) [reset = 0x0000]
        1. Table 12. CONFIG Register Field Descriptions
      5. 9.6.5 GAIN Register (address = 0x04) [reset = 0x---]
        1. Table 13. GAIN Register Field Descriptions
      6. 9.6.6 TRIGGER Register (address = 0x05) [reset = 0x0000]
        1. Table 14. TRIGGER Register Field Descriptions
      7. 9.6.7 BRDCAST Register (address = 0x6) [reset = 0x0000]
        1. Table 15. BRDCAST Register Field Descriptions
      8. 9.6.8 STATUS Register (address = 0x7) [reset = 0x0000]
        1. Table 16. STATUS Register Field Descriptions
      9. 9.6.9 DACx Register (address = 0x8 to 0xF) [reset = 0x0000 or 0x8000]
        1. Table 17. DACx Register Field Descriptions
  10. 10Application and Implementation
    1. 10.1 Application Information
      1. 10.1.1 Interfacing to a Microcontroller
      2. 10.1.2 Programmable Current Source Circuit
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
      3. 10.2.3 Application Curve
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  13. 13デバイスおよびドキュメントのサポート
    1. 13.1 ドキュメントのサポート
      1. 13.1.1 関連資料
    2. 13.2 関連リンク
    3. 13.3 ドキュメントの更新通知を受け取る方法
    4. 13.4 コミュニティ・リソース
    5. 13.5 商標
    6. 13.6 静電気放電に関する注意事項
    7. 13.7 Glossary
  14. 14メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

8.5 Electrical Characteristics

all minimum and maximum specifications at VDD= 2.7 V to 5.5 V, VIO = 1.7 V to 5.5 V, VREFIN = 1.25 V to 5.5 V, RLOAD = 2 kΩ to GND, CLOAD = 200 pF to GND, digital inputs at VIO or GND, and TA = –40°C to +125°C (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
STATIC PERFORMANCE(1)
Resolution DAC80504 16 Bits
DAC70504 14
DAC60504 12
INL Integral nonlinearity DAC80504 ±0.5 ±1 LSB
DAC70504 ±0.5 ±1
DAC60504 ±0.5 ±1
DNL Differential nonlinearity DAC80504, specified 16-bit monotonic ±0.5 ±1 LSB
DAC70504, specified 14-bit monotonic ±0.5 ±1
DAC60504, specified 12-bit monotonic ±0.5 ±1
TUE Total unadjusted error ±0.05 ±0.1 %FSR
Offset error ±0.75 ±1.5 mV
Zero-code error DAC code = zero scale 0.5 1.5 mV
Full-scale error ±0.05 ±0.1 %FSR
Gain error ±0.05 ±0.1 %FSR
Offset error drift ±1 µV/°C
Zero-code error drift ±2 µV/°C
Full-scale error drift ±2 ppm of FSR/°C
Gain error drift ±1 ppm of FSR/°C
Output voltage drift over time TA = 25°C, DAC code = midscale, 1600 hours 20 ppm of FSR
OUTPUT CHARACTERISTICS
Voltage range Gain = 2 (BUFF-GAIN = 1, REF-DIV = 0) 0 2 × VREF V
Gain = 1 (BUFF-GAIN = 1, REF-DIV = 1) 0 VREF
Gain = ½ (BUFF-GAIN = 0, REF-DIV = 1) 0 ½ × VREF
Output voltage headroom to GND or VDD (unloaded) 0.004 V
to GND or VDD (–5 mA ≤ IOUT ≤ 5 mA) 0.15
to GND or VDD (–10 mA ≤ IOUT ≤ 10 mA) 0.3
to GND or VDD (–20 mA ≤ IOUT ≤ 20 mA) 0.5
Short circuit current(2) DAC code = full scale, output shorted to GND 30 mA
DAC code = zero scale, output shorted to VDD 35
Load regulation DAC code = midscale, -10 mA ≤ IOUT ≤ 10 mA 85 µV/mA
Maximum capacitive load(3) RLOAD = ∞ 0 2 nF
RLOAD = 2 kΩ 0 10
DC output impedance DAC code = midscale 0.085 Ω
DAC code at GND or VDD 15
DYNAMIC PERFORMANCE
Output voltage settling time ¼ to ¾ scale and ¾ to ¼ scale settling time to ±2 LSB, VDD = 5.5 V, VREFIN = 2.5 V, gain = 2 5 µs
Slew rate VDD = 5.5 V, VREFIN = 2.5 V, gain = 2 1.8 V/µs
Power-up time DACx-PWDWN 1 to 0 transition, DAC code = full scale, VDD = 5.5 V, VREFIN = 2.5 V, gain = 2(4) 12 µs
Power-up glitch magnitude DAC code = zero scale, VDD = 5.5 V, VREFIN = 2.5 V, gain = 2. CLOAD = 50 pF 25 mV
Output noise 0.1 Hz to 10 Hz, DAC code = midscale, VDD = 5.5 V, VREFIN = 2.5 V, gain = 2 14 µVPP
Output noise density 1 kHz, DAC code = midscale, VDD = 5.5 V, VREFIN = 2.5 V, gain = 2 78 nV/√Hz
10 kHz, DAC code = midscale, VDD = 5.5 V, VREFIN = 2.5 V, gain = 2 74
1 kHz, DAC code = full scale, VDD = 5.5 V, VREFIN = 2.5 V, gain = 1 55
10 kHz, DAC code = full scale, VDD = 5.5 V, VREFIN = 2.5 V, gain = 1 50
AC PSRR DAC code = midscale, frequency = 60 Hz,
amplitude = 200 mVPP superimposed on VDD 		85 dB
DC PSRR DAC code = midscale, VDD = 5 V ± 10% 10 µV/V
Code change glitch impulse 1 LSB change around major carrier 4 nV-s
Channel-to-channel ac crosstalk DAC code = midscale. Code 32 to full-scale swing on adjacent channel 0.2 nV-s
Channel-to-channel dc crosstalk Measured channel at midscale, adjacent channel at full scale 5 µV
Measured channel at midscale, all other channels at full scale 10
Digital feedthrough DAC code = midscale. fSCLK = 1 MHz, SDO disabled 0.1 nV-s
EXTERNAL REFERENCE INPUT
Reference input current VREFIN = 2.5 V 25 µA
Reference input impedance 100 kΩ
Reference input capacitance 5 pF
INTERNAL REFERENCE
VREFOUT Reference output voltage TA = 25°C 2.495 2.5 2.505 V
Reference output drift 2 5 ppm/°C
Reference output impedance 0.1 Ω
Reference output noise 0.1 Hz to 10 Hz 15 µVPP
Reference output noise density 10 kHz, REFLOAD = 10 nF 130 nV/√Hz
Reference load current ±5 mA
Reference load regulation Source and sink 100 µV/mA
Reference line regulation 20 µV/V
Reference output drift over time TA = 25°C, 1600 hours 4.8 ppm
Reference thermal hysteresis First cycle 50 ppm
Additional cycle 18
DIGITAL INPUTS
VIH High-level input voltage 0.7 × VIO V
VIL Low-level input voltage 0.3 × VIO V
Input current ±2 µA
Input pin capacitance 2 pF
DIGITAL OUTPUTS
VOH High-level output voltage ILOAD = 0.2 mA VIO – 0.4 V
VOL Low-level output voltage ILOAD = –0.2 mA 0.4 V
Output pin capacitance 4 pF
POWER SUPPLY REQUIREMENTS
IDD VDD supply current Active mode, internal reference enabled, gain = 1, DAC code = full scale, outputs unloaded, SPI static 2.8 3.6 mA
Active mode, internal reference disabled, gain = 1, DAC code = full scale, outputs unloaded, SPI static 2.3 3
Power-down 15 µA
IIO VIO supply current 2 3 µA
(1) Static performance specified with DAC outputs unloaded for all gain options, unless otherwise noted. End point fit between codes. 16-bit: Code 256 to 65280, 14-bit: Code 128 to 16127, 12-bit: Code 16 to 4031.
(2) Temporary overload condition protection. Junction temperature can be exceeded during current limit. Operation above the specified maximum junction temperature may impair device reliability.
(3) Specified by design and characterization. Not tested during production.
(4) Time to exit DAC power-down mode. Measured from CS rising edge to 90% of DAC final value.