JAJSE78C August   2017  – January 2019 DAC60504 , DAC70504 , DAC80504

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     Device Images
      1.      ブロック概略図
  4. 4 改訂履歴
  5. 5 概要（続き）
  6. 6 Device Comparison Table
  7. 7 Pin Configuration and Functions
    1.     Pin Functions
  8. 8 Specifications
    1. 8.1 Absolute Maximum Ratings
    2. 8.2 ESD Ratings
    3. 8.3 Recommended Operating Conditions
    4. 8.4 Thermal Information
    5. 8.5 Electrical Characteristics
    6. 8.6 Typical Characteristics
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 Digital-to-Analog Converter (DAC)
        1. 9.3.1.1 DAC Transfer Function
        2. 9.3.1.2 Output Amplifiers
        3. 9.3.1.3 DAC Register Structure
          1. 9.3.1.3.1 DAC Register Synchronous and Asynchronous Updates
          2. 9.3.1.3.2 Broadcast DAC Register
      2. 9.3.2 Internal Reference
        1. 9.3.2.1 Reference Divider
        2. 9.3.2.2 Solder Heat Reflow
      3. 9.3.3 Device Reset Options
        1. 9.3.3.1 Power-on-Reset (POR)
        2. 9.3.3.2 Software Reset
    4. 9.4 Device Functional Modes
      1. 9.4.1 Stand-Alone Operation
      2. 9.4.2 Daisy-Chain Operation
      3. 9.4.3 Frame Error Checking
      4. 9.4.4 Power-Down Mode
    5. 9.5 Programming
    6. 9.6 Register Map
      1. 9.6.1 NOP Register (address = 0x00) [reset = 0x0000]
        1. Table 9. NOP Register Field Descriptions
      2. 9.6.2 DEVICE ID Register (address = 0x01) [reset = 0x---]
        1. Table 10. DEVICE ID Field Descriptions
      3. 9.6.3 SYNC Register (address = 0x2) [reset = 0xFF00]
        1. Table 11. SYNC Register Field Descriptions
      4. 9.6.4 CONFIG Register (address = 0x3) [reset = 0x0000]
        1. Table 12. CONFIG Register Field Descriptions
      5. 9.6.5 GAIN Register (address = 0x04) [reset = 0x---]
        1. Table 13. GAIN Register Field Descriptions
      6. 9.6.6 TRIGGER Register (address = 0x05) [reset = 0x0000]
        1. Table 14. TRIGGER Register Field Descriptions
      7. 9.6.7 BRDCAST Register (address = 0x6) [reset = 0x0000]
        1. Table 15. BRDCAST Register Field Descriptions
      8. 9.6.8 STATUS Register (address = 0x7) [reset = 0x0000]
        1. Table 16. STATUS Register Field Descriptions
      9. 9.6.9 DACx Register (address = 0x8 to 0xF) [reset = 0x0000 or 0x8000]
        1. Table 17. DACx Register Field Descriptions
  10. 10Application and Implementation
    1. 10.1 Application Information
      1. 10.1.1 Interfacing to a Microcontroller
      2. 10.1.2 Programmable Current Source Circuit
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
      3. 10.2.3 Application Curve
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  13. 13デバイスおよびドキュメントのサポート
    1. 13.1 ドキュメントのサポート
      1. 13.1.1 関連資料
    2. 13.2 関連リンク
    3. 13.3 ドキュメントの更新通知を受け取る方法
    4. 13.4 コミュニティ・リソース
    5. 13.5 商標
    6. 13.6 静電気放電に関する注意事項
    7. 13.7 Glossary
  14. 14メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

7 Pin Configuration and Functions

RTE Package
16-Pin WQFN
Top View

Pin Functions

PIN TYPE DESCRIPTION
NAME NO.
REF 1 I/O When using internal reference, this is the reference output voltage pin (default). When using an external reference, this is the reference input pin to the device.
OUT0 2 O Analog output voltage from DAC 0.
OUT1 3 O Analog output voltage from DAC 1.
OUT2 4 O Analog output voltage from DAC 2.
OUT3 5 O Analog output voltage from DAC 3.
GND 6 GND Ground reference point for all circuitry on the device.
VDD 7 PWR Analog supply voltage (2.7 V to 5.5 V).
GAIN 8 I Sets the gain configuration after a power-up or reset event. When tied to GND, the initial buffer amplifier gain for all four channels is set to 1. When tied to VIO the initial buffer amplifier gain is 2. Changing the state of this pin after power-up does not affect the device operation.
RSTSEL 9 I Reset select pin. When tied to GND all four DACs reset to zero scale. When connected to VIO all four DACs reset to midscale.
REFDIV 10 I Sets the reference divider configuration after a power-up or reset event. When tied to GND, the reference voltage is not divided down. When tied to VIO the reference voltage is divided by 2. Changing the state of this pin after power-up does not affect the device operation.
LDAC 11 I A high-to-low transition on the LDAC pin causes the DAC outputs of those channels configured in synchronous mode to update simultaneously. The pin can be tied permanently to GND.
CS 12 I Active low serial data enable. This input is the frame synchronization signal for the serial data. When the signal goes low, it enables the serial interface input shift register.
SCLK 13 I Serial interface clock.
SDI 14 I Serial interface data input. Data are clocked into the input shift register on each falling edge of the SCLK pin.
SDO/ALARM 15 O Serial interface data output (default). The SDO pin is in high impedance when CS pin is high. Data are clocked out of the input shift register on either rising or falling edges of the SCLK pin as specified by the FSDO bit. Alternatively the pin can be configured as an ALARM open-drain output to indicate a CRC or reference alarm event. If configured as ALARM a 10 kΩ, pull-up resistor to VIO is required.
VIO 16 PWR IO supply voltage (1.7 V to 5.5 V). This pin sets the I/O operating voltage for the serial interface.
Thermal Pad – – The thermal pad is located on the bottom-side of the QFN package. The thermal pad should be connected to any internal PCB ground plane using multiple vias for good thermal performance.