9.1.1.1 Supply Voltage

The internal reference features an extremely low dropout voltage. It can be operated with a supply of only 5 mV above the reference output voltage in an unloaded condition. For loaded conditions, see the Load Regulation section. The stability of the internal reference with variations in supply voltage (line regulation, dc PSRR) is also exceptional. Within the specified supply voltage range of 2.7 V to 5.5 V, the variation at V_REFIN/V_REFOUT is typically 50 μV/V; see Figure 7.

9.1.1.2 Temperature Drift

The internal reference is designed to exhibit minimal drift error, defined as the change in reference output voltage over varying temperature. The drift is calculated using the box method described by Equation 3:

Equation 3.

where:

V_{REF_MAX} = maximum reference voltage observed within temperature range T_RANGE.
V_{REF_MIN} = minimum reference voltage observed within temperature range T_RANGE.
V_REF = 2.5 V, target value for reference output voltage.
T_RANGE = the characterized range from –40°C to 125°C (165°C range)

The internal reference features an exceptional typical drift coefficient of 4 ppm/°C from –40°C to 125°C. Characterizing a large number of units, a maximum drift coefficient of 10 ppm/°C is observed. Temperature drift results are summarized in Figure 3.

9.1.1.3 Noise Performance

Typical 0.1-Hz to 10-Hz voltage noise and noise spectral density performance are listed in the Electrical Characteristics. Additional filtering can be used to improve output noise levels, although care should be taken to ensure the output impedance does not degrade the ac performance. The output noise spectrum at the V_REFIN/V_REFOUT pin, both unloaded and with an external 4.7-µF load capacitor, is shown in Figure 6. Internal reference noise impacts the DAC output noise when the internal reference is used.

9.1.1.4 Load Regulation

Load regulation is defined as the change in reference output voltage as a result of changes in load current. The load regulation of the internal reference is measured using force and sense contacts as shown in Figure 95. The force and sense lines reduce the impact of contact and trace resistance, resulting in accurate measurement of the load regulation contributed solely by the internal reference. Measurement results are shown in Figure 4. Force and sense lines should be used for applications that require improved load regulation.

Figure 95. Accurate Load Regulation of the DAC756x-Q1, DAC816x-Q1, and DAC856x-Q1 Internal Reference

9.1.1.5 Thermal Hysteresis

Thermal hysteresis for a reference is defined as the change in output voltage after operating the device at 25°C, cycling the device through the operating temperature range, and returning to 25°C. Hysteresis is expressed by Equation 4:

Equation 4.

where:

V_HYST = thermal hysteresis.
V_{REF_PRE} = output voltage measured at 25°C pre-temperature cycling.
V_{REF_POST} = output voltage measured after the device cycles through the temperature range of –40°C to
aaa 125°C, and returns to 25°C.
V_{REF_NOM} = 2.5 V, target value for reference output voltage.

9.2.1.1 Design Requirements

The design uses a DAC and a current-or-voltage output driver to create a discrete analog output design that can output either voltage or current from the same pin while focusing on high-accuracy specifications. The choice of the DAC8563-Q1 device takes advantage of its 16-bit resolution as well as its low typical offset error of 1 mV and gain error of 0.01% FSR. The choice of the XTR300 device is based on its strong dc performance, having a typical error of 400 µV and 0.04% FSR gain error. The XTR300 device allows a variety of both current and voltage outputs on the same pin while providing load monitoring and error status pins.

The power-on reset-to-midscale feature of the DAC8563-Q1 makes the bipolar output of the XTR300 power up at 0 V or 0 A. If using a unipolar output, the recommended device to achieve a system power-on output of 0 V, 0 A or 4 mA is the DAC8562-Q1 device.

A recommendation for minimizing the introduction of errors into the system is to use ±0.01% tolerance RG and RSET resistors. The bypass capacitors on AV_DD, VREF, V+ and V– should have values between 100 nF and 10 µF. Smaller capacitors filter fast low-energy transients, whereas the large capacitors filter the slow high-energy transients. If there is an expectation of both types of signals in the system, the recommendation is to use a pair of small and large values as shown on the AV_DD pin of the DAC8563-Q1 device in Figure 96.

9.2.1.2 Detailed Design Procedure

When configured for voltage mode, the output of the instrumentation amplifier (IA), internal to the XTR300 device, is routed to the SET pin. The SET output provides feedback for the IA based on the IA input voltage. The feedback from the IA provides high-impedance remote sensing of the voltage at the output load. Using the output voltage can overcome errors from PCB traces and protection component impedances. The DAC provides a unipolar input voltage to the VIN pin of the XTR300 device. The XTR300 device offsets the VDAC range by a negative V_REF and amplifies the difference by a value set by the R_G and R_SET resistors, as shown in Equation 5.

Equation 5.

When configured for current mode, the XTR300 routes the internal output of its current copy circuitry to the SET pin. This provides feedback for the internal OPA driver based on 1 / 10th of the output current, resulting in a voltage-to-current transfer function. Generating bipolar current outputs from the single-ended DAC output voltage, VDAC, requires the application of an offset to the XTR300 SET pin. Connect the R_SET resistor from the SET pin to V_REF to apply the offset and obtain the transfer function shown in Equation 6.

Equation 6.

The desired output ranges for VDAC and V_REF voltages determine the R_SET and R_G resistor values, calculated using Equation 7 and Equation 8. The system design requires a VDAC voltage range of 0.04 V to 4.96 V in order to operate the DAC8563-Q1 in the specified linear output range from codes 512 to 65 024.

Equation 7.

Equation 8.

I_MON and IA_OUT accomplish load monitoring. The sizing of R_IMON and R_IA determine the monitoring output voltage across the resistors. Size the resistors according to Equation 9 and Equation 10 and the expected output load current I_DRV.

Equation 9.

Equation 10.

For more detailed information about the design procedure of this circuit and how to isolate it, see Two-Channel Source/Sink Combined Voltage & Current Output, Isolated, EMC/EMI Tested Reference Design (TIDU434).

9.2.1.3 Application Curves

Figure 97 shows the transfer function for the bipolar ±10 V voltage range. This design also supports output voltage ranges of 0–5 V, 0–10 V and ±5 V. Figure 98 shows the transfer function for the unipolar 0–24 mA current range. This design also supports output current ranges of ±24 mA and 4 mA–20 mA.

Figure 97. Output Voltage vs Input Code

Figure 98. Output Current vs Input Code