8.3.1 Digital-to-Analog Converter (DAC)

The DAC756x-Q1, DAC816x-Q1, and DAC856x-Q1 architecture consists of two string DACs, each followed by an output buffer amplifier. The devices include an internal 2.5-V reference with 4-ppm/°C temperature drift performance. Figure 88 shows a principal block diagram of the DAC architecture.

Figure 88. DAC Architecture

The input coding to the DAC756x-Q1, DAC816x-Q1, and DAC856x-Q1 devices is straight binary, so the ideal output voltage is given by Equation 1:

Equation 1.

where:

n = resolution in bits; either 12 (DAC756x-Q1), 14 (DAC816x-Q1) or 16 (DAC856x-Q1)
D_IN = decimal equivalent of the binary code that is loaded to the DAC register. D_IN ranges from 0 to 2ⁿ – 1.
V_REF = DAC reference voltage; either V_REFOUT from the internal 2.5-V reference or V_REFIN from an
aaa external reference.
Gain = 1 by default when internal reference is disabled (using external reference), and gain = 2 by default
aaa when using internal reference. Gain can also be manually set to either 1 or 2 using the gain register.
aaa See the Gain Function section for more information.

8.3.1.1 Resistor String

The resistor string section is shown in Figure 89. It is simply a string of resistors, each of value R. The code loaded into the DAC register determines at which node on the string the voltage is tapped off to be fed into the output amplifier by closing one of the switches connecting the string to the amplifier. The resistor string architecture results in monotonicity. The R_DIVIDER switch is controlled by the gain registers (see the Gain Function section). Because the output amplifier has a gain of 2, R_DIVIDER is not shorted when the DAC-n gain is set to 1 (default if internal reference is disabled), and is shorted when the DAC-n gain is set to 2 (default if internal reference is enabled).

Figure 89. Resistor String

8.3.2 Internal Reference

The DAC756x-Q1, DAC816x-Q1, and DAC856x-Q1 devices include a 2.5-V internal reference that is disabled by default. The internal reference is externally available at the V_REFIN/V_REFOUT pin. The internal reference output voltage is 2.5 V and can sink and source up to 20 mA.

A minimum 150-nF capacitor is recommended between the reference output and GND for noise filtering.

The internal reference of the DAC756x-Q1, DAC816x-Q1, and DAC856x-Q1 devices is a bipolar transistor-based precision band-gap voltage reference. Figure 90 shows the basic band-gap topology. Transistors Q₁ and Q₂ are biased such that the current density of Q₁ is greater than that of Q₂. The difference of the two base-emitter voltages (V_BE1 – V_BE2) has a positive temperature coefficient and is forced across resistor R₁. This voltage is amplified and added to the base-emitter voltage of Q₂, which has a negative temperature coefficient. The resulting output voltage is virtually independent of temperature. The short-circuit current is limited by design to approximately 100 mA.

Figure 90. Band-Gap Reference Simplified Schematic

8.3.3 Power-On Reset

8.3.3.3 Power-On Reset (POR) Levels

When the device powers up, a POR circuit sets the device in default mode as shown in Table 4. The POR circuit requires specific AV_DD levels, as indicated in Figure 91, to ensure discharging of internal capacitors and to reset the device on power up. In order to ensure a power-on reset, AV_DD must be below 0.7 V for at least 1 ms. When AV_DD drops below 2.2 V but remains above 0.7 V (shown as the undefined region), the device may or may not reset under all specified temperature and power-supply conditions. In this case, TI recommends a power-on reset. When AV_DD remains above 2.2 V, a power-on reset does not occur.

Figure 91. Relevant Voltage Levels for POR Circuit

8.4.1 Power-Down Modes

The DAC756x-Q1, DAC816x-Q1, and DAC856x-Q1 devices have two separate sets of power-down commands. One set is for the DAC channels and the other set is for the internal reference. The internal reference is forced to a powered-down state while both DAC channels are powered down, and is only enabled if any DAC channel is also in the normal mode of operation. For more information on the internal reference control, see the Internal Reference Enable Register section.

8.4.1.1 DAC Power-Down Commands

The DAC756x-Q1, DAC816x-Q1, and DAC856x-Q1 DACs use four modes of operation. These modes are accessed by setting the serial interface command bits to 100. Once the command bits are set correctly, the four different power-down modes are software programmable by setting bits DB5 and DB4 in the shift register. Table 5 and Table 6 show the different power-down options. For more information on how to set the DAC operating mode see Table 17.

Table 5. DAC-n Operating Modes

DB5	DB4	DAC MODES OF OPERATION
0	0	Selected DACs power up (normal mode, default)
0	1	Selected DACs power down, output 1 kΩ to GND
1	0	Selected DACs power down, output 100 kΩ to GND
1	1	Selected DACs power down, output Hi-Z to GND

Table 6. DAC-n Selection for Operating Modes

DAC-B (DB1), DAC-A (DB0)	OPERATING MODE
0	DAC-n does not change operating mode
1	DAC-n operating mode set to value on PD1 and PD0

It is possible to write to the DAC register or buffer of the DAC channel that is powered down. When the DAC channel is then powered up, it powers up to this new value.

The advantage of the available power-down modes is that the output impedance of the device is known while it is in power-down mode. As described in Table 5, there are three different power-down options. V_OUT can be connected internally to GND through a 1-kΩ resistor, a 100-kΩ resistor, or open-circuited (Hi-Z). The DAC power-down circuitry is shown in Figure 92.

Figure 92. Output Stage

8.4.2 Gain Function

The gain register controls the GAIN setting in the DAC transfer function:

Equation 2.

The DAC756x-Q1, DAC816x-Q1, and DAC856x-Q1 devices have a gain register for each channel. The gain for each channel, in Equation 2, is either 1 or 2. This gain is automatically set to 2 when using the internal reference, and is automatically set to 1 when the internal reference is disabled (default). However, each channel can have either gain by setting the registers appropriately. The gain registers are accessible by setting the serial interface command bits to 000, address bits to 010, and using DB1 for DAC-B and DB0 for DAC-A. See Table 7 and Table 17 for the full command structure. The gain registers are automatically reset to provide either gain of 1 or 2 when the internal reference is powered off or on, respectively. After the reference is powered off or on, the gain register is again accessible to change the gain.

8.4.3 Software Reset Function

The DAC756x-Q1, DAC816x-Q1, and DAC856x-Q1 devices contain a software reset feature. The software reset function is accessed by setting the serial interface command bits to 101. The software reset command contains two reset modes which are software-programmable by setting bit DB0 in the shift register. Table 8 and Table 17 show the available software reset commands.

8.4.4 Internal Reference Enable Register

The internal reference in the DAC756x-Q1, DAC816x-Q1, and DAC856x-Q1 devices is disabled by default for debugging, evaluation purposes, or when using an external reference. The internal reference can be powered up and powered down by setting the serial interface command bits to 111 and configuring DB0 (see Table 9). The internal reference is forced to a powered down state while both DAC channels are powered down, and can only be enabled if any DAC channel is in normal mode of operation. During the time that the internal reference is disabled, the DAC functions normally using an external reference. At this point, the internal reference is disconnected from the V_REFIN/V_REFOUT pin (Hi-Z output).

8.4.5 CLR Functionality

The edge-triggered CLR pin can be used to set the input and DAC registers immediately according to Table 10. When the CLR pin receives a falling edge signal the clear mode is activated and changes the DAC output voltages accordingly. The device exits clear mode on the 24^th falling edge of the next write to the device. If the CLR pin receives a falling edge signal during a write sequence in normal operation, the clear mode is activated and changes the input and DAC registers immediately according to Table 10.

8.4.6 LDAC Functionality

The DAC756x-Q1, DAC816x-Q1, and DAC856x-Q1 devices offer both a software and hardware simultaneous update and control function. The DAC double-buffered architecture has been designed so that new data can be entered for each DAC without disturbing the analog outputs.

DAC756x-Q1, DAC816x-Q1, and DAC856x-Q1 data updates can be performed either in synchronous or in asynchronous mode.

In asynchronous mode, the LDAC pin is used as a negative edge-triggered timing signal for simultaneous DAC updates. Multiple single-channel writes can be done in order to set different channel buffers to desired values and then make a falling edge on LDAC pin to simultaneously update the DAC output registers. Data buffers of all channels must be loaded with desired data before an LDAC falling edge. After a high-to-low LDAC transition, all DACs are simultaneously updated with the last contents of the corresponding data buffers. If the content of a data buffer is not changed, the corresponding DAC output remains unchanged after the LDAC pin is triggered. LDAC must be returned high before the next serial command is initiated.

In synchronous mode, data are updated with the falling edge of the 24^th SCLK cycle, which follows a falling edge of SYNC. For such synchronous updates, the LDAC pin is not required, and it must be connected to GND permanently or asserted and held low before sending commands to the device.

Alternatively, all DAC outputs can be updated simultaneously using the built-in software function of LDAC. The LDAC register offers additional flexibility and control by allowing the selection of which DAC channel(s) should be updated simultaneously when the LDAC pin is being brought low. The LDAC register is loaded with a 2-bit word (DB1 and DB0) using command bits C2, C1, and C0 (see Table 17). The default value for each bit, and therefore for each DAC channel, is zero. If the LDAC register bit is set to 1, it overrides the LDAC pin (the LDAC pin is internally tied low for that particular DAC channel) and this DAC channel updates synchronously after the falling edge of the 24^th SCLK cycle. However, if the LDAC register bit is set to 0, the DAC channel is controlled by the LDAC pin.

The combination of software and hardware simultaneous update functions is particularly useful in applications when updating a DAC channel, while keeping the other channel unaffected; see Table 11 and Table 17 for more information.

8.5.1 SYNC Interrupt

In a normal write sequence, the SYNC line stays low for at least 24 falling edges of SCLK and the addressed DAC register updates on the 24^th falling edge. However, if SYNC is brought high before the 23^rd falling edge, it acts as an interrupt to the write sequence; the shift register resets and the write sequence is discarded. Neither an update of the data buffer contents, DAC register contents, nor a change in the operating mode occurs (as shown in Figure 93).

Figure 93. SYNC Interrupt Facility

8.5.2 DAC Register Configuration

When the DAC registers are being written to, the DAC756x-Q1, DAC816x-Q1, and DAC856x-Q1 devices receive all 24 bits of data, ignore DB23 and DB22, and decode the next three bits (DB21 to DB19) in order to determine the DAC operating or control mode (see Table 12). Bits DB18 to DB16 are used to address the DAC channels (see Table 13).

When writing to the DAC input registers the next 16, 14, or 12 bits of data that follow are decoded by the DAC to determine the equivalent analog output (see Table 14 through Table 16). The data format is straight binary, with all 0s corresponding to 0-V output and all 1s corresponding to full-scale output. For all documentation purposes, the data format and representation used here is a true 16-bit pattern (that is, FFFFh data word for full scale) that the DAC756x-Q1, DAC816x-Q1, and DAC856x-Q1 devices require.

Table 17. Command Matrix for the DAC756x-Q1, DAC816x-Q1, and DAC856x-Q1 Devices