JAJSE84D June   2017  – August 2018 DAC60508 , DAC70508 , DAC80508

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     Device Images
      1.      ブロック概略図
  4. 4 改訂履歴
  5. 5 概要（続き）
  6. 6 Device Comparison Table
  7. 7 Pin Configuration and Functions
    1.     Pin Functions
  8. 8 Specifications
    1. 8.1 Absolute Maximum Ratings
    2. 8.2 ESD Ratings
    3. 8.3 Recommended Operating Conditions
    4. 8.4 Thermal Information
    5. 8.5 Electrical Characteristics
    6. 8.6 Typical Characteristics
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 Digital-to-Analog Converter (DAC) Architecture
        1. 9.3.1.1 DAC Transfer Function
        2. 9.3.1.2 Output Amplifiers
        3. 9.3.1.3 DAC Register Structure
          1. 9.3.1.3.1 DAC Register Synchronous and Asynchronous Updates
          2. 9.3.1.3.2 Broadcast DAC Register
          3. 9.3.1.3.3 CLEAR Operation (DACx0508C only)
      2. 9.3.2 Internal Reference
        1. 9.3.2.1 Reference Divider
        2. 9.3.2.2 Solder Heat Reflow
      3. 9.3.3 Device Reset Options
        1. 9.3.3.1 Power-on-Reset (POR)
        2. 9.3.3.2 Software Reset
    4. 9.4 Device Functional Modes
      1. 9.4.1 Stand-Alone Operation
      2. 9.4.2 Daisy-Chain Operation
      3. 9.4.3 Frame Error Checking
      4. 9.4.4 Power-Down Mode
    5. 9.5 Programming
    6. 9.6 Register Map
      1. 9.6.1 NOP Register (address = 0x00) [reset = 0x0000]
        1. Table 9. NOP Register Field Descriptions
      2. 9.6.2 DEVICE ID Register (address = 0x01) [reset = 0x---]
        1. Table 10. DEVICE ID Field Descriptions
      3. 9.6.3 SYNC Register (address = 0x2) [reset = 0xFF00]
        1. Table 11. SYNC Register Field Descriptions
      4. 9.6.4 CONFIG Register (address = 0x3) [reset = 0x0000]
        1. Table 12. CONFIG Register Field Descriptions
      5. 9.6.5 GAIN Register (address = 0x04) [reset = 0x---]
        1. Table 13. GAIN Register Field Descriptions
      6. 9.6.6 TRIGGER Register (address = 0x05) [reset = 0x0000]
        1. Table 14. TRIGGER Register Field Descriptions
      7. 9.6.7 BRDCAST Register (address = 0x6) [reset = 0x0000]
        1. Table 15. BRDCAST Register Field Descriptions
      8. 9.6.8 STATUS Register (address = 0x7) [reset = 0x0000]
        1. Table 16. STATUS Register Field Descriptions
      9. 9.6.9 DACx Register (address = 0x8 to 0xF) [reset = 0x0000 or 0x8000]
        1. Table 17. DACx Register Field Descriptions
  10. 10Application and Implementation
    1. 10.1 Application Information
      1. 10.1.1 Interfacing to Microcontroller
      2. 10.1.2 Programmable Current Source Circuit
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
      3. 10.2.3 Application Curve
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Examples
  13. 13デバイスおよびドキュメントのサポート
    1. 13.1 関連リンク
    2. 13.2 ドキュメントの更新通知を受け取る方法
    3. 13.3 コミュニティ・リソース
    4. 13.4 商標
    5. 13.5 静電気放電に関する注意事項
    6. 13.6 Glossary
  14. 14メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

9.3.1.3.3 CLEAR Operation (DACx0508C only)

The CLR pin enables a simultaneous update of multiple DAC channels to the clear value: zero code (DACx0508ZC) or midscale code (DACx0508MC). DAC channels 0 through 3 and channels 4 through 7 can be independently configured to update or remain unaffected by the CLR pin by setting the corresponding CLR-MSK bit. A CLR pin logic low forces those DAC channels that have been configured for clear operation to clear the contents of their buffer and active registers to the clear value and sets the analog outputs accordingly, regardless of their synchronization setting. Those channels not configured for clear operation retain their buffer and active register contents as well as the corresponding analog outputs even if a clear command is issued. While the CLR pin is kept low, register writes to the DAC data registers of those channels set for clear operation are ignored. A logic high on the CLR pin causes the device to exit clear mode.