SLASF62 June   2024 DAC80516

ADVANCE INFORMATION  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Thermal Information
    5. 5.5  Electrical Characteristics
    6. 5.6  Timing Requirements - I2C Standard Mode
    7. 5.7  Timing Requirements - I2C Fast Mode
    8. 5.8  Timing Requirements - I2C Fast Mode Plus
    9. 5.9  Timing Requirements - SPI
    10. 5.10 Switching Characteristics
    11. 5.11 Timing Diagrams
    12. 5.12 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Digital-to-Analog Converter (DAC) Architecture
        1. 6.3.1.1 DAC Register Structure
          1. 6.3.1.1.1 DAC Synchronous Operation
          2. 6.3.1.1.2 DAC Buffer Amplifier
          3. 6.3.1.1.3 DAC Transfer Function
      2. 6.3.2 Internal Reference
      3. 6.3.3 Power-On Reset (POR)
    4. 6.4 Device Functional Modes
      1. 6.4.1 Clear Mode
    5. 6.5 Programming
      1. 6.5.1 I2C Serial Interface
        1. 6.5.1.1 I2C Bus Overview
        2. 6.5.1.2 I2C Bus Definitions
        3. 6.5.1.3 I2C Target Address Selection
        4. 6.5.1.4 I2C Read and Write Operations
        5. 6.5.1.5 I2C General-Call Reset
      2. 6.5.2 Serial Peripheral Interface (SPI)
        1. 6.5.2.1 SPI Bus Overview
  8. 7 Register Map
    1. 7.1 DAC80516 Registers
  9. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Bipolar Voltage Output
    2. 8.2 Typical Application
      1. 8.2.1 Programmable High-Current Voltage Output Circuit
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
        3. 8.2.1.3 Application Curve
    3. 8.3 Initialization Setup
    4. 8.4 Power Supply Recommendations
    5. 8.5 Layout
      1. 8.5.1 Layout Guidelines
      2. 8.5.2 Layout Examples
  10. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information
    1. 11.1 Tape and Reel Information

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発注情報

7.1 DAC80516 Registers

7.1.1 NOP Register (Offset = 0h) [Reset = 0000h]

Figure 7-1 NOP Register
15 14 13 12 11 10 9 8
NOP[15:0]
W-0h
7 6 5 4 3 2 1 0
NOP[15:0]
W-0h
Table 7-2 NOP Register Field Descriptions
Bit Field Type Reset Description
15:0 NOP[15:0] W 0h
No Operation (NOP).

7.1.2 DEVICE_ID Register (Offset = 1h) [Reset = 8516h]

Figure 7-2 DEVICE_ID Register
15 14 13 12 11 10 9 8
CHIP_ID[15:0]
R-85h
7 6 5 4 3 2 1 0
CHIP_ID[15:0]
R-16h
Table 7-3 DEVICE_ID Register Field Descriptions
Bit Field Type Reset Description
15:0 CHIP_ID[15:0] R 8516h Device Chip ID.
Device Chip ID loaded from OTP.

7.1.3 VERSION_ID Register (Offset = 2h) [Reset = 0000h]

Figure 7-3 VERSION_ID Register
15 14 13 12 11 10 9 8
RESERVED
R-0h
7 6 5 4 3 2 1 0
RESERVED VERSION_ID[2:0]
R-0h R-0h
Table 7-4 VERSION_ID Register Field Descriptions
Bit Field Type Reset Description
15:3 RESERVED R 0h
2:0 VERSION_ID[2:0] R 0h Device Version ID.
Device Version ID loaded from OTP.

7.1.4 PWDWN Register (Offset = 3h) [Reset = FFFFh]

Figure 7-4 PWDWN Register
15 14 13 12 11 10 9 8
OUT15_PWDWN OUT14_PWDWN OUT13_PWDWN OUT12_PWDWN OUT11_PWDWN OUT10_PWDWN OUT9_PWDWN OUT8_PWDWN
R/W-1h R/W-1h R/W-1h R/W-1h R/W-1h R/W-1h R/W-1h R/W-1h
7 6 5 4 3 2 1 0
OUT7_PWDWN OUT6_PWDWN OUT5_PWDWN OUT4_PWDWN OUT3_PWDWN OUT2_PWDWN OUT1_PWDWN OUT0_PWDWN
R/W-1h R/W-1h R/W-1h R/W-1h R/W-1h R/W-1h R/W-1h R/W-1h
Table 7-5 PWDWN Register Field Descriptions
Bit Field Type Reset Description
15 OUT15_PWDWN R/W 1h
OUT15 power down bit.
0h = This DAC is enabled
1h = This DAC is disabled in a low-power mode
14 OUT14_PWDWN R/W 1h
OUT14 power down bit.
0h = This DAC is enabled
1h = This DAC is disabled in a low-power mode
13 OUT13_PWDWN R/W 1h
OUT13 power down bit.
0h = This DAC is enabled
1h = This DAC is disabled in a low-power mode
12 OUT12_PWDWN R/W 1h
OUT12 power down bit.
0h = This DAC is enabled
1h = This DAC is disabled in a low-power mode
11 OUT11_PWDWN R/W 1h
OUT11 power down bit.
0h = This DAC is enabled
1h = This DAC is disabled in a low-power mode
10 OUT10_PWDWN R/W 1h
OUT10 power down bit.
0h = This DAC is enabled
1h = This DAC is disabled in a low-power mode
9 OUT9_PWDWN R/W 1h
OUT9 power down bit.
0h = This DAC is enabled
1h = This DAC is disabled in a low-power mode
8 OUT8_PWDWN R/W 1h
OUT8 power down bit.
0h = This DAC is enabled
1h = This DAC is disabled in a low-power mode
7 OUT7_PWDWN R/W 1h
OUT7 power down bit.
0h = This DAC is enabled
1h = This DAC is disabled in a low-power mode
6 OUT6_PWDWN R/W 1h
OUT6 power down bit.
0h = This DAC is enabled
1h = This DAC is disabled in a low-power mode
5 OUT5_PWDWN R/W 1h
OUT5 power down bit.
0h = This DAC is enabled
1h = This DAC is disabled in a low-power mode
4 OUT4_PWDWN R/W 1h
OUT4 power down bit.
0h = This DAC is enabled
1h = This DAC is disabled in a low-power mode
3 OUT3_PWDWN R/W 1h
OUT3 power down bit.
0h = This DAC is enabled
1h = This DAC is disabled in a low-power mode
2 OUT2_PWDWN R/W 1h
OUT2 power down bit.
0h = This DAC is enabled
1h = This DAC is disabled in a low-power mode
1 OUT1_PWDWN R/W 1h
OUT1 power down bit.
0h = This DAC is enabled
1h = This DAC is disabled in a low-power mode
0 OUT0_PWDWN R/W 1h
OUT0 power down bit.
0h = This DAC is enabled
1h = This DAC is disabled in a low-power mode

7.1.5 DAC_GAIN Register (Offset = 4h) [Reset = 0000h]

Figure 7-5 DAC_GAIN Register
15 14 13 12 11 10 9 8
RESERVED
R-0h
7 6 5 4 3 2 1 0
RESERVED OUT_QUAD3_GAIN OUT_QUAD2_GAIN OUT_QUAD1_GAIN OUT_QUAD0_GAIN
R-0h R/W-0h R/W-0h R/W-0h R/W-0h
Table 7-6 DAC_GAIN Register Field Descriptions
Bit Field Type Reset Description
15:4 RESERVED R 0h
3 OUT_QUAD3_GAIN R/W 0h QUAD-3 VREF Gain.
VREF gain setting for OUT12, OUT13, OUT14, OUT15.
0h = This group of DACs is in 0V – 1 × VREF output range
1h = This group of DACs is in 0V – 2 × VREF output range
2 OUT_QUAD2_GAIN R/W 0h QUAD-2 VREF Gain.
VREF gain setting for OUT8, OUT9, OUT10, OUT11.
0h = This group of DACs is in 0V – 1 × VREF output range
1h = This group of DACs is in 0V – 2 × VREF output range
1 OUT_QUAD1_GAIN R/W 0h QUAD-1 VREF Gain.
VREF gain setting for OUT4, OUT5, OUT6, OUT7.
0h = This group of DACs is in 0V – 1 × VREF output range
1h = This group of DACs is in 0V – 2 × VREF output range
0 OUT_QUAD0_GAIN R/W 0h QUAD-0 VREF Gain.
VREF gain setting for OUT0, OUT1, OUT2, OUT3.
0h = This group of DACs is in 0V – 1 × VREF output range
1h = This group of DACs is in 0V – 2 × VREF output range

7.1.6 TRIGGER Register (Offset = 5h) [Reset = 0000h]

Figure 7-6 TRIGGER Register
15 14 13 12 11 10 9 8
LDAC_
OUT15_OUT14		 LDAC_
OUT13_OUT12		 LDAC_
OUT11_OUT10		 LDAC_
OUT9_OUT8		 LDAC_
OUT7_OUT6		 LDAC_
OUT5_OUT4		 LDAC_
OUT3_OUT2		 LDAC_
OUT1_OUT0
W-0h W-0h W-0h W-0h W-0h W-0h W-0h W-0h
7 6 5 4 3 2 1 0
RESERVED SOFT_RST[3:0]
R-0h W-0h
Table 7-7 TRIGGER Register Field Descriptions
Bit Field Type Reset Description
15 LDAC_OUT15_OUT14 W 0h Software DAC trigger.
Transfers DAC data from OUT15 and OUT14 buffer registers to active registers on channels that are configured in synchronous mode. This bit self-clears when action is completed.
0h = No action
1h = Transfer DAC data. This bit clears when action is completed.
14 LDAC_OUT13_OUT12 W 0h Software DAC trigger.
Transfers DAC data from OUT13 and OUT12 buffer registers to active registers on channels that are configured in synchronous mode. This bit self-clears when action is completed.
0h = No action
1h = Transfer DAC data. This bit clears when action is completed.
13 LDAC_OUT11_OUT10 W 0h Software DAC trigger.
Transfers DAC data from OUT11 and OUT10 buffer registers to active registers on channels that are configured in synchronous mode. This bit self-clears when action is completed.
0h = No action
1h = Transfer DAC data. This bit clears when action is completed.
12 LDAC_OUT9_OUT8 W 0h Software DAC trigger.
Transfers DAC data from OUT9 and OUT8 buffer registers to active registers on channels that are configured in synchronous mode. This bit self-clears when action is completed.
0h = No action
1h = Transfer DAC data. This bit clears when action is completed.
11 LDAC_OUT7_OUT6 W 0h Software DAC trigger.
Transfers DAC data from OUT7 and OUT6 buffer registers to active registers on channels that are configured in synchronous mode. This bit self-clears when action is completed.
0h = No action
1h = Transfer DAC data. This bit clears when action is completed.
10 LDAC_OUT5_OUT4 W 0h Software DAC trigger.
Transfers DAC data from OUT5 and OUT4 buffer registers to active registers on channels that are configured in synchronous mode. This bit self-clears when action is completed.
0h = No action
1h = Transfer DAC data. This bit clears when action is completed.
9 LDAC_OUT3_OUT2 W 0h Software DAC trigger.
Transfers DAC data from OUT3 and OUT2 buffer registers to active registers on channels that are configured in synchronous mode. This bit self-clears when action is completed.
0h = No action
1h = Transfer DAC data. This bit clears when action is completed.
8 LDAC_OUT1_OUT0 W 0h Software DAC trigger.
Transfers DAC data from OUT1 and OUT0 buffer registers to active registers on channels that are configured in synchronous mode. This bit self-clears when action is completed.
0h = No action
1h = Transfer DAC data. This bit clears when action is completed.
7:4 RESERVED R 0h
3:0 SOFT_RST[3:0] W 0h Software device reset.

Ah = Software Reset. Executes a full power-on-reset. Resets the device and all registers to the default power-on-reset state. Auto clears with execution.

7.1.7 BCAST_DAC_DATA Register (Offset = 6h) [Reset = 0000h]

Figure 7-7 BCAST_DAC_DATA Register
15 14 13 12 11 10 9 8
DATA[15:0]
R/W-0h
7 6 5 4 3 2 1 0
DATA[15:0]
R/W-0h
Table 7-8 BCAST_DAC_DATA Register Field Descriptions
Bit Field Type Reset Description
15:0 DATA[15:0] R/W 0h A write to this register sets all DAC buffer and active register values to the specified code on output channels for which the broadcast enable bit is set. Otherwise, that channel's buffer and active registers are unchanged.

7.1.8 STATUS Register (Offset = 7h) [Reset = 4008h]

Figure 7-8 STATUS Register
15 14 13 12 11 10 9 8
RESERVED
R-40h
7 6 5 4 3 2 1 0
RESERVED GDAC_SC_STS
R-04h R-0h
Table 7-9 STATUS Register Field Descriptions
Bit Field Type Reset Description
15:1 RESERVED R 2004h
0 GDAC_SC_STS R 0h Global DAC short circuit status.
Global DAC short circuit status bit. This bit is the OR function of all DACn_SC_STS bits. DACn_SC_STS bits are located in DAC_STATUS register having one bit per DAC.
0h = No DAC output channels are in a short-circuit condition
1h = At least one DAC output channel is in a short-circuit condition

7.1.9 SDO_EN Register (Offset = 8h) [Reset = 0000h]

Figure 7-9 SDO_EN Register
15 14 13 12 11 10 9 8
RESERVED
R-0h
7 6 5 4 3 2 1 0
RESERVED FSDO SDO_EN
R-0h R/W-0h R/W-0h
Table 7-10 SDO_EN Register Field Descriptions
Bit Field Type Reset Description
15:2 RESERVED R 0h
1 FSDO R/W 0h Fast SDO.
Allows faster SPI bus speeds by sending the SDO data out one SCLK half-cycle earlier. SDI latching edge is always SCLK falling edge regardless of this setting. FSDO is ignored when SDO_EN is disabled.
0h = SDO drives MSB when chip select goes low and then updates on each SCLK rising edge (opposite edge of SDI latching edge).
1h = SDO drives MSB when chip select goes low and then updates on each SCLK falling edge (same edge as SDI latching edge)
0 SDO_EN R/W 0h SDO enable.
Enable the SDO pin driver. When enabled, SDO is enabled for read and writes whenever SPI chip-select pin is low. SDO is always disabled in I2C mode regardless of this bit setting.
0h = SDO disabled
1h = SDO enabled during read and write operations

7.1.10 GEN_CONFIG Register (Offset = 9h) [Reset = 0014h]

Figure 7-10 GEN_CONFIG Register
15 14 13 12 11 10 9 8
RESERVED
R-0h
7 6 5 4 3 2 1 0
RESERVED FLEXIO_OUT_POL FLEXIO_OUT_ODE RESERVED REF_PWDWN RESERVED FLEXIO_FUNC
R-0h R/W-0h R/W-1h R-0h R/W-1h R-0h R/W-0h
Table 7-11 GEN_CONFIG Register Field Descriptions
Bit Field Type Reset Description
15:6 RESERVED R 0h
5 FLEXIO_OUT_POL R/W 0h FLEXIO pin polarity.
Set the FLEXIO pin output active state (when pin is configured as GPIO).
0h = FLEXIO digital pin outputs 0V if GPIO_DATA is set to 0x00h, and VIO if GPIO_DATA is set to 0x01h
1h = FLEXIO digital pin outputs VIO if GPIO_DATA is set to 0x00h, and 0V if GPIO_DATA is set to 0x01h
4 FLEXIO_OUT_ODE R/W 1h FLEXIO open drain enable.
Set the FLEXIO pin drive mode (when pin is configured as GPIO). Do not raise pin above the absolute maximum ratings with respect to VIO voltage. Bit is ignored if pin is not configured as a digital output.
0h = FLEXIO pin output is push-pull
1h = FLEXIO pin output is open-drain
3 RESERVED R 0h
2 REF_PWDWN R/W 1h Disable internal reference.
Set to enable or disable the internal voltage reference.
0h = Internal reference enabled
1h = Internal reference disabled
1 RESERVED R 0h
0 FLEXIO_FUNC R/W 0h FLEXIO pin function.
Sets the function of FLEXIO pin.
0h = GPIO. In this mode, the pin operates as a GPIO and the GPIO_DATA register is used to support GPIO functionality.
1h = CLEAR pin. In this mode, the pin operates as an active-low DAC Clear input pin.

7.1.11 SYNC_EN Register (Offset = Ah) [Reset = 0000h]

Figure 7-11 SYNC_EN Register
15 14 13 12 11 10 9 8
OUT15_
SYNC_EN		 OUT14_
SYNC_EN		 OUT13_
SYNC_EN		 OUT12_
SYNC_EN		 OUT11_
SYNC_EN		 OUT10_
SYNC_EN		 OUT9_
SYNC_EN		 OUT8_
SYNC_EN
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h
7 6 5 4 3 2 1 0
OUT7_
SYNC_EN		 OUT6_
SYNC_EN		 OUT5_
SYNC_EN		 OUT4_
SYNC_EN		 OUT3_
SYNC_EN		 OUT2_
SYNC_EN		 OUT1_
SYNC_EN		 OUT0_
SYNC_EN
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h
Table 7-12 SYNC_EN Register Field Descriptions
Bit Field Type Reset Description
15 OUT15_SYNC_EN R/W 0h Synchronous mode enable.
Enable or disable synchronous mode.
0h = Set this DAC into asynchronous mode (DAC active register updates when DAC buffer is updated)
1h = Set this DAC into synchronous mode (DAC active register updates with DAC trigger)
14 OUT14_SYNC_EN R/W 0h Synchronous mode enable.
Enable or disable synchronous mode.
0h = Set this DAC into asynchronous mode (DAC active register updates when DAC buffer is updated)
1h = Set this DAC into synchronous mode (DAC active register updates with DAC trigger)
13 OUT13_SYNC_EN R/W 0h Synchronous mode enable.
Enable or disable synchronous mode.
0h = Set this DAC into asynchronous mode (DAC active register updates when DAC buffer is updated)
1h = Set this DAC into synchronous mode (DAC active register updates with DAC trigger)
12 OUT12_SYNC_EN R/W 0h Synchronous mode enable.
Enable or disable synchronous mode.
0h = Set this DAC into asynchronous mode (DAC active register updates when DAC buffer is updated)
1h = Set this DAC into synchronous mode (DAC active register updates with DAC trigger)
11 OUT11_SYNC_EN R/W 0h Synchronous mode enable.
Enable or disable synchronous mode.
0h = Set this DAC into asynchronous mode (DAC active register updates when DAC buffer is updated)
1h = Set this DAC into synchronous mode (DAC active register updates with DAC trigger)
10 OUT10_SYNC_EN R/W 0h Synchronous mode enable.
Enable or disable synchronous mode.
0h = Set this DAC into asynchronous mode (DAC active register updates when DAC buffer is updated)
1h = Set this DAC into synchronous mode (DAC active register updates with DAC trigger)
9 OUT9_SYNC_EN R/W 0h Synchronous mode enable.
Enable or disable synchronous mode.
0h = Set this DAC into asynchronous mode (DAC active register updates when DAC buffer is updated)
1h = Set this DAC into synchronous mode (DAC active register updates with DAC trigger)
8 OUT8_SYNC_EN R/W 0h Synchronous mode enable.
Enable or disable synchronous mode.
0h = Set this DAC into asynchronous mode (DAC active register updates when DAC buffer is updated)
1h = Set this DAC into synchronous mode (DAC active register updates with DAC trigger)
7 OUT7_SYNC_EN R/W 0h Synchronous mode enable.
Enable or disable synchronous mode.
0h = Set this DAC into asynchronous mode (DAC active register updates when DAC buffer is updated)
1h = Set this DAC into synchronous mode (DAC active register updates with DAC trigger)
6 OUT6_SYNC_EN R/W 0h Synchronous mode enable.
Enable or disable synchronous mode.
0h = Set this DAC into asynchronous mode (DAC active register updates when DAC buffer is updated)
1h = Set this DAC into synchronous mode (DAC active register updates with DAC trigger)
5 OUT5_SYNC_EN R/W 0h Synchronous mode enable.
Enable or disable synchronous mode.
0h = Set this DAC into asynchronous mode (DAC active register updates when DAC buffer is updated)
1h = Set this DAC into synchronous mode (DAC active register updates with DAC trigger)
4 OUT4_SYNC_EN R/W 0h Synchronous mode enable.
Enable or disable synchronous mode.
0h = Set this DAC into asynchronous mode (DAC active register updates when DAC buffer is updated)
1h = Set this DAC into synchronous mode (DAC active register updates with DAC trigger)
3 OUT3_SYNC_EN R/W 0h Synchronous mode enable.
Enable or disable synchronous mode.
0h = Set this DAC into asynchronous mode (DAC active register updates when DAC buffer is updated)
1h = Set this DAC into synchronous mode (DAC active register updates with DAC trigger)
2 OUT2_SYNC_EN R/W 0h Synchronous mode enable.
Enable or disable synchronous mode.
0h = Set this DAC into asynchronous mode (DAC active register updates when DAC buffer is updated)
1h = Set this DAC into synchronous mode (DAC active register updates with DAC trigger)
1 OUT1_SYNC_EN R/W 0h Synchronous mode enable.
Enable or disable synchronous mode.
0h = Set this DAC into asynchronous mode (DAC active register updates when DAC buffer is updated)
1h = Set this DAC into synchronous mode (DAC active register updates with DAC trigger)
0 OUT0_SYNC_EN R/W 0h Synchronous mode enable.
Enable or disable synchronous mode.
0h = Set this DAC into asynchronous mode (DAC active register updates when DAC buffer is updated)
1h = Set this DAC into synchronous mode (DAC active register updates with DAC trigger)

7.1.12 BCAST_EN Register (Offset = Bh) [Reset = FFFFh]

Figure 7-12 BCAST_EN Register
15 14 13 12 11 10 9 8
OUT15_
BCAST_EN		 OUT14_
BCAST_EN		 OUT13_
BCAST_EN		 OUT12_
BCAST_EN		 OUT11_
BCAST_EN		 OUT10_
BCAST_EN		 OUT9_
BCAST_EN		 OUT8_
BCAST_EN
R/W-1h R/W-1h R/W-1h R/W-1h R/W-1h R/W-1h R/W-1h R/W-1h
7 6 5 4 3 2 1 0
OUT7_
BCAST_EN		 OUT6_
BCAST_EN		 OUT5_
BCAST_EN		 OUT4_
BCAST_EN		 OUT3_
BCAST_EN		 OUT2_
BCAST_EN		 OUT1_
BCAST_EN		 OUT0_
BCAST_EN
R/W-1h R/W-1h R/W-1h R/W-1h R/W-1h R/W-1h R/W-1h R/W-1h
Table 7-13 BCAST_EN Register Field Descriptions
Bit Field Type Reset Description
15 OUT15_BCAST_EN R/W 1h
Enable or disable broadcast mode.
0h = Ignore broadcast writes on this DAC
1h = Allow broadcast writes on this DAC
14 OUT14_BCAST_EN R/W 1h
Enable or disable broadcast mode.
0h = Ignore broadcast writes on this DAC
1h = Allow broadcast writes on this DAC
13 OUT13_BCAST_EN R/W 1h
Enable or disable broadcast mode.
0h = Ignore broadcast writes on this DAC
1h = Allow broadcast writes on this DAC
12 OUT12_BCAST_EN R/W 1h
Enable or disable broadcast mode.
0h = Ignore broadcast writes on this DAC
1h = Allow broadcast writes on this DAC
11 OUT11_BCAST_EN R/W 1h
Enable or disable broadcast mode.
0h = Ignore broadcast writes on this DAC
1h = Allow broadcast writes on this DAC
10 OUT10_BCAST_EN R/W 1h
Enable or disable broadcast mode.
0h = Ignore broadcast writes on this DAC
1h = Allow broadcast writes on this DAC
9 OUT9_BCAST_EN R/W 1h
Enable or disable broadcast mode.
0h = Ignore broadcast writes on this DAC
1h = Allow broadcast writes on this DAC
8 OUT8_BCAST_EN R/W 1h
Enable or disable broadcast mode.
0h = Ignore broadcast writes on this DAC
1h = Allow broadcast writes on this DAC
7 OUT7_BCAST_EN R/W 1h
Enable or disable broadcast mode.
0h = Ignore broadcast writes on this DAC
1h = Allow broadcast writes on this DAC
6 OUT6_BCAST_EN R/W 1h
Enable or disable broadcast mode.
0h = Ignore broadcast writes on this DAC
1h = Allow broadcast writes on this DAC
5 OUT5_BCAST_EN R/W 1h
Enable or disable broadcast mode.
0h = Ignore broadcast writes on this DAC
1h = Allow broadcast writes on this DAC
4 OUT4_BCAST_EN R/W 1h
Enable or disable broadcast mode.
0h = Ignore broadcast writes on this DAC
1h = Allow broadcast writes on this DAC
3 OUT3_BCAST_EN R/W 1h
Enable or disable broadcast mode.
0h = Ignore broadcast writes on this DAC
1h = Allow broadcast writes on this DAC
2 OUT2_BCAST_EN R/W 1h
Enable or disable broadcast mode.
0h = Ignore broadcast writes on this DAC
1h = Allow broadcast writes on this DAC
1 OUT1_BCAST_EN R/W 1h
Enable or disable broadcast mode.
0h = Ignore broadcast writes on this DAC
1h = Allow broadcast writes on this DAC
0 OUT0_BCAST_EN R/W 1h
Enable or disable broadcast mode.
0h = Ignore broadcast writes on this DAC
1h = Allow broadcast writes on this DAC

7.1.13 CLEAR Register (Offset = Ch) [Reset = 0000h]

Figure 7-13 CLEAR Register
15 14 13 12 11 10 9 8
OUT15_
SW_CLR		 OUT14_
SW_CLR		 OUT13_
SW_CLR		 OUT12_
SW_CLR		 OUT11_
SW_CLR		 OUT10_
SW_CLR		 OUT9_
SW_CLR		 OUT8_
SW_CLR
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h
7 6 5 4 3 2 1 0
OUT7_
SW_CLR		 OUT6_
SW_CLR		 OUT5_
SW_CLR		 OUT4_
SW_CLR		 OUT3_
SW_CLR		 OUT2_
SW_CLR		 OUT1_
SW_CLR		 OUT0_
SW_CLR
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h
Table 7-14 CLEAR Register Field Descriptions
Bit Field Type Reset Description
15 OUT15_SW_CLR R/W 0h Software clear enable bit.
Forces DAC to enter clear state. DAC uses clear code that is specified in clear state.
0h = Restore this DAC to normal operation
1h = Force this DAC into clear state
14 OUT14_SW_CLR R/W 0h Software clear enable bit.
Forces DAC to enter clear state. DAC uses clear code that is specified in clear state.
0h = Restore this DAC to normal operation
1h = Force this DAC into clear state
13 OUT13_SW_CLR R/W 0h Software clear enable bit.
Forces DAC to enter clear state. DAC uses clear code that is specified in clear state.
0h = Restore this DAC to normal operation
1h = Force this DAC into clear state
12 OUT12_SW_CLR R/W 0h Software clear enable bit.
Forces DAC to enter clear state. DAC uses clear code that is specified in clear state.
0h = Restore this DAC to normal operation
1h = Force this DAC into clear state
11 OUT11_SW_CLR R/W 0h Software clear enable bit.
Forces DAC to enter clear state. DAC uses clear code that is specified in clear state.
0h = Restore this DAC to normal operation
1h = Force this DAC into clear state
10 OUT10_SW_CLR R/W 0h Software clear enable bit.
Forces DAC to enter clear state. DAC uses clear code that is specified in clear state.
0h = Restore this DAC to normal operation
1h = Force this DAC into clear state
9 OUT9_SW_CLR R/W 0h Software clear enable bit.
Forces DAC to enter clear state. DAC uses clear code that is specified in clear state.
0h = Restore this DAC to normal operation
1h = Force this DAC into clear state
8 OUT8_SW_CLR R/W 0h Software clear enable bit.
Forces DAC to enter clear state. DAC uses clear code that is specified in clear state.
0h = Restore this DAC to normal operation
1h = Force this DAC into clear state
7 OUT7_SW_CLR R/W 0h Software clear enable bit.
Forces DAC to enter clear state. DAC uses clear code that is specified in clear state.
0h = Restore this DAC to normal operation
1h = Force this DAC into clear state
6 OUT6_SW_CLR R/W 0h Software clear enable bit.
Forces DAC to enter clear state. DAC uses clear code that is specified in clear state.
0h = Restore this DAC to normal operation
1h = Force this DAC into clear state
5 OUT5_SW_CLR R/W 0h Software clear enable bit.
Forces DAC to enter clear state. DAC uses clear code that is specified in clear state.
0h = Restore this DAC to normal operation
1h = Force this DAC into clear state
4 OUT4_SW_CLR R/W 0h Software clear enable bit.
Forces DAC to enter clear state. DAC uses clear code that is specified in clear state.
0h = Restore this DAC to normal operation
1h = Force this DAC into clear state
3 OUT3_SW_CLR R/W 0h Software clear enable bit.
Forces DAC to enter clear state. DAC uses clear code that is specified in clear state.
0h = Restore this DAC to normal operation
1h = Force this DAC into clear state
2 OUT2_SW_CLR R/W 0h Software clear enable bit.
Forces DAC to enter clear state. DAC uses clear code that is specified in clear state.
0h = Restore this DAC to normal operation
1h = Force this DAC into clear state
1 OUT1_SW_CLR R/W 0h Software clear enable bit.
Forces DAC to enter clear state. DAC uses clear code that is specified in clear state.
0h = Restore this DAC to normal operation
1h = Force this DAC into clear state
0 OUT0_SW_CLR R/W 0h Software clear enable bit.
Forces DAC to enter clear state. DAC uses clear code that is specified in clear state.
0h = Restore this DAC to normal operation
1h = Force this DAC into clear state

7.1.14 CLEAR_PIN_MASK Register (Offset = Dh) [Reset = 0000h]

Figure 7-14 CLEAR_PIN_MASK Register
15 14 13 12 11 10 9 8
OUT15_
HW_CLR_MASK		 OUT14_
HW_CLR_MASK		 OUT13_
HW_CLR_MASK		 OUT12_
HW_CLR_MASK		 OUT11_
HW_CLR_MASK		 OUT10_
HW_CLR_MASK		 OUT9_
HW_CLR_MASK		 OUT8_
HW_CLR_MASK
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h
7 6 5 4 3 2 1 0
OUT7_
HW_CLR_MASK		 OUT6_
HW_CLR_MASK		 OUT5_
HW_CLR_MASK		 OUT4_
HW_CLR_MASK		 OUT3_
HW_CLR_MASK		 OUT2_
HW_CLR_MASK		 OUT1_
HW_CLR_MASK		 OUT0_
HW_CLR_MASK
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h
Table 7-15 CLEAR_PIN_MASK Register Field Descriptions
Bit Field Type Reset Description
15 OUT15_HW_CLR_MASK R/W 0h Mask bit for CLEAR (FLEXIO) pin.
0h = CLEAR pin affects this DAC channel
1h = CLEAR pin does not affect this DAC channel
14 OUT14_HW_CLR_MASK R/W 0h Mask bit for CLEAR (FLEXIO) pin.
0h = CLEAR pin affects this DAC channel
1h = CLEAR pin does not affect this DAC channel
13 OUT13_HW_CLR_MASK R/W 0h Mask bit for CLEAR (FLEXIO) pin.
0h = CLEAR pin affects this DAC channel
1h = CLEAR pin does not affect this DAC channel
12 OUT12_HW_CLR_MASK R/W 0h Mask bit for CLEAR (FLEXIO) pin.
0h = CLEAR pin affects this DAC channel
1h = CLEAR pin does not affect this DAC channel
11 OUT11_HW_CLR_MASK R/W 0h Mask bit for CLEAR (FLEXIO) pin.
0h = CLEAR pin affects this DAC channel
1h = CLEAR pin does not affect this DAC channel
10 OUT10_HW_CLR_MASK R/W 0h Mask bit for CLEAR (FLEXIO) pin.
0h = CLEAR pin affects this DAC channel
1h = CLEAR pin does not affect this DAC channel
9 OUT9_HW_CLR_MASK R/W 0h Mask bit for CLEAR (FLEXIO) pin.
0h = CLEAR pin affects this DAC channel
1h = CLEAR pin does not affect this DAC channel
8 OUT8_HW_CLR_MASK R/W 0h Mask bit for CLEAR (FLEXIO) pin.
0h = CLEAR pin affects this DAC channel
1h = CLEAR pin does not affect this DAC channel
7 OUT7_HW_CLR_MASK R/W 0h Mask bit for CLEAR (FLEXIO) pin.
0h = CLEAR pin affects this DAC channel
1h = CLEAR pin does not affect this DAC channel
6 OUT6_HW_CLR_MASK R/W 0h Mask bit for CLEAR (FLEXIO) pin.
0h = CLEAR pin affects this DAC channel
1h = CLEAR pin does not affect this DAC channel
5 OUT5_HW_CLR_MASK R/W 0h Mask bit for CLEAR (FLEXIO) pin.
0h = CLEAR pin affects this DAC channel
1h = CLEAR pin does not affect this DAC channel
4 OUT4_HW_CLR_MASK R/W 0h Mask bit for CLEAR (FLEXIO) pin.
0h = CLEAR pin affects this DAC channel
1h = CLEAR pin does not affect this DAC channel
3 OUT3_HW_CLR_MASK R/W 0h Mask bit for CLEAR (FLEXIO) pin.
0h = CLEAR pin affects this DAC channel
1h = CLEAR pin does not affect this DAC channel
2 OUT2_HW_CLR_MASK R/W 0h Mask bit for CLEAR (FLEXIO) pin.
0h = CLEAR pin affects this DAC channel
1h = CLEAR pin does not affect this DAC channel
1 OUT1_HW_CLR_MASK R/W 0h Mask bit for CLEAR (FLEXIO) pin.
0h = CLEAR pin affects this DAC channel
1h = CLEAR pin does not affect this DAC channel
0 OUT0_HW_CLR_MASK R/W 0h Mask bit for CLEAR (FLEXIO) pin.
0h = CLEAR pin affects this DAC channel
1h = CLEAR pin does not affect this DAC channel

7.1.15 BCAST_CLR_DATA Register (Offset = Eh) [Reset = 0000h]

Figure 7-15 BCAST_CLR_DATA Register
15 14 13 12 11 10 9 8
DATA[15:0]
R/W-0h
7 6 5 4 3 2 1 0
DATA[15:0]
R/W-0h
Table 7-16 BCAST_CLR_DATA Register Field Descriptions
Bit Field Type Reset Description
15:0 DATA[15:0] R/W 0h A write to this register sets all DAC clear code register values to the specified code on output channels for which the broadcast enable bit is set.

7.1.16 RESET_FLAGS Register (Offset = Fh) [Reset = 000Fh]

Figure 7-16 RESET_FLAGS Register
15 14 13 12 11 10 9 8
RESERVED
R-0h
7 6 5 4 3 2 1 0
RESERVED VDD_
COLLAPSE_
FLAG		 RSTPIN_
FLAG		 VIO_
FLAG		 PORBASE_
FLAG
R-0h W-1h W-1h W-1h W-1h
Table 7-17 RESET_FLAGS Register Field Descriptions
Bit Field Type Reset Description
4 VDD_COLLAPSE_FLAG W 1h Write to 0 to detect a VDD collapse event, at which time this flag is automatically set to 1. VDD collapse occurs when VDD reaches to within 1V of the VREF voltage.
3 RSTPIN_FLAG W 1h Write to 0 to detect a RESET pin reset event, at which time this flag is automatically set to 1.
2 VIO_FLAG W 1h Write to 0 to detect a VIO reset event, at which time this flag is automatically set to 1. VIO reset event occurs as a result of VIO dropping to less than the POR threshold voltage.
1 PORBASE_FLAG W 1h Write to 0 to detect a POR-base reset event, at which time this flag is automatically set to 1. A POR-base reset event occurs as a result of VDD dropping to less than the POR threshold voltage.

7.1.17 OUT0_BUFFER_CODE Register (Offset = 10h) [Reset = 0000h]

Figure 7-17 OUT0_BUFFER_CODE Register
15 14 13 12 11 10 9 8
DATA[15:0]
R/W-0h
7 6 5 4 3 2 1 0
DATA[15:0]
R/W-0h
Table 7-18 OUT0_BUFFER_CODE Register Field Descriptions
Bit Field Type Reset Description
15:0 DATA[15:0] R/W 0h Code for OUT0 buffer register, unipolar straight binary format.

7.1.18 OUT1_BUFFER_CODE Register (Offset = 11h) [Reset = 0000h]

Figure 7-18 OUT1_BUFFER_CODE Register
15 14 13 12 11 10 9 8
DATA[15:0]
R/W-0h
7 6 5 4 3 2 1 0
DATA[15:0]
R/W-0h
Table 7-19 OUT1_BUFFER_CODE Register Field Descriptions
Bit Field Type Reset Description
15:0 DATA[15:0] R/W 0h Code for OUT1 buffer register, unipolar straight binary format.

7.1.19 OUT2_BUFFER_CODE Register (Offset = 12h) [Reset = 0000h]

Figure 7-19 OUT2_BUFFER_CODE Register
15 14 13 12 11 10 9 8
DATA[15:0]
R/W-0h
7 6 5 4 3 2 1 0
DATA[15:0]
R/W-0h
Table 7-20 OUT2_BUFFER_CODE Register Field Descriptions
Bit Field Type Reset Description
15:0 DATA[15:0] R/W 0h Code for OUT2 buffer register, unipolar straight binary format.

7.1.20 OUT3_BUFFER_CODE Register (Offset = 13h) [Reset = 0000h]

Figure 7-20 OUT3_BUFFER_CODE Register
15 14 13 12 11 10 9 8
DATA[15:0]
R/W-0h
7 6 5 4 3 2 1 0
DATA[15:0]
R/W-0h
Table 7-21 OUT3_BUFFER_CODE Register Field Descriptions
Bit Field Type Reset Description
15:0 DATA[15:0] R/W 0h Code for OUT3 buffer register, unipolar straight binary format.

7.1.21 OUT4_BUFFER_CODE Register (Offset = 14h) [Reset = 0000h]

Figure 7-21 OUT4_BUFFER_CODE Register
15 14 13 12 11 10 9 8
DATA[15:0]
R/W-0h
7 6 5 4 3 2 1 0
DATA[15:0]
R/W-0h
Table 7-22 OUT4_BUFFER_CODE Register Field Descriptions
Bit Field Type Reset Description
15:0 DATA[15:0] R/W 0h Code for OUT4 buffer register, unipolar straight binary format.

7.1.22 OUT5_BUFFER_CODE Register (Offset = 15h) [Reset = 0000h]

Figure 7-22 OUT5_BUFFER_CODE Register
15 14 13 12 11 10 9 8
DATA[15:0]
R/W-0h
7 6 5 4 3 2 1 0
DATA[15:0]
R/W-0h
Table 7-23 OUT5_BUFFER_CODE Register Field Descriptions
Bit Field Type Reset Description
15:0 DATA[15:0] R/W 0h Code for OUT5 buffer register, unipolar straight binary format.

7.1.23 OUT6_BUFFER_CODE Register (Offset = 16h) [Reset = 0000h]

Figure 7-23 OUT6_BUFFER_CODE Register
15 14 13 12 11 10 9 8
DATA[15:0]
R/W-0h
7 6 5 4 3 2 1 0
DATA[15:0]
R/W-0h
Table 7-24 OUT6_BUFFER_CODE Register Field Descriptions
Bit Field Type Reset Description
15:0 DATA[15:0] R/W 0h Code for OUT6 buffer register, unipolar straight binary format.

7.1.24 OUT7_BUFFER_CODE Register (Offset = 17h) [Reset = 0000h]

Figure 7-24 OUT7_BUFFER_CODE Register
15 14 13 12 11 10 9 8
DATA[15:0]
R/W-0h
7 6 5 4 3 2 1 0
DATA[15:0]
R/W-0h
Table 7-25 OUT7_BUFFER_CODE Register Field Descriptions
Bit Field Type Reset Description
15:0 DATA[15:0] R/W 0h Code for OUT7 buffer register, unipolar straight binary format.

7.1.25 OUT8_BUFFER_CODE Register (Offset = 18h) [Reset = 0000h]

Figure 7-25 OUT8_BUFFER_CODE Register
15 14 13 12 11 10 9 8
DATA[15:0]
R/W-0h
7 6 5 4 3 2 1 0
DATA[15:0]
R/W-0h
Table 7-26 OUT8_BUFFER_CODE Register Field Descriptions
Bit Field Type Reset Description
15:0 DATA[15:0] R/W 0h Code for OUT8 buffer register, unipolar straight binary format.

7.1.26 OUT9_BUFFER_CODE Register (Offset = 19h) [Reset = 0000h]

Figure 7-26 OUT9_BUFFER_CODE Register
15 14 13 12 11 10 9 8
DATA[15:0]
R/W-0h
7 6 5 4 3 2 1 0
DATA[15:0]
R/W-0h
Table 7-27 OUT9_BUFFER_CODE Register Field Descriptions
Bit Field Type Reset Description
15:0 DATA[15:0] R/W 0h Code for OUT9 buffer register, unipolar straight binary format.

7.1.27 OUT10_BUFFER_CODE Register (Offset = 1Ah) [Reset = 0000h]

Figure 7-27 OUT10_BUFFER_CODE Register
15 14 13 12 11 10 9 8
DATA[15:0]
R/W-0h
7 6 5 4 3 2 1 0
DATA[15:0]
R/W-0h
Table 7-28 OUT10_BUFFER_CODE Register Field Descriptions
Bit Field Type Reset Description
15:0 DATA[15:0] R/W 0h Code for OUT10 buffer register, unipolar straight binary format.

7.1.28 OUT11_BUFFER_CODE Register (Offset = 1Bh) [Reset = 0000h]

Figure 7-28 OUT11_BUFFER_CODE Register
15 14 13 12 11 10 9 8
DATA[15:0]
R/W-0h
7 6 5 4 3 2 1 0
DATA[15:0]
R/W-0h
Table 7-29 OUT11_BUFFER_CODE Register Field Descriptions
Bit Field Type Reset Description
15:0 DATA[15:0] R/W 0h Code for OUT11 buffer register, unipolar straight binary format.

7.1.29 OUT12_BUFFER_CODE Register (Offset = 1Ch) [Reset = 0000h]

Figure 7-29 OUT12_BUFFER_CODE Register
15 14 13 12 11 10 9 8
DATA[15:0]
R/W-0h
7 6 5 4 3 2 1 0
DATA[15:0]
R/W-0h
Table 7-30 OUT12_BUFFER_CODE Register Field Descriptions
Bit Field Type Reset Description
15:0 DATA[15:0] R/W 0h Code for OUT12 buffer register, unipolar straight binary format.

7.1.30 OUT13_BUFFER_CODE Register (Offset = 1Dh) [Reset = 0000h]

Figure 7-30 OUT13_BUFFER_CODE Register
15 14 13 12 11 10 9 8
DATA[15:0]
R/W-0h
7 6 5 4 3 2 1 0
DATA[15:0]
R/W-0h
Table 7-31 OUT13_BUFFER_CODE Register Field Descriptions
Bit Field Type Reset Description
15:0 DATA[15:0] R/W 0h Code for OUT13 buffer register, unipolar straight binary format.

7.1.31 OUT14_BUFFER_CODE Register (Offset = 1Eh) [Reset = 0000h]

Figure 7-31 OUT14_BUFFER_CODE Register
15 14 13 12 11 10 9 8
DATA[15:0]
R/W-0h
7 6 5 4 3 2 1 0
DATA[15:0]
R/W-0h
Table 7-32 OUT14_BUFFER_CODE Register Field Descriptions
Bit Field Type Reset Description
15:0 DATA[15:0] R/W 0h Code for OUT14 buffer register, unipolar straight binary format.

7.1.32 OUT15_BUFFER_CODE Register (Offset = 1Fh) [Reset = 0000h]

Figure 7-32 OUT15_BUFFER_CODE Register
15 14 13 12 11 10 9 8
DATA[15:0]
R/W-0h
7 6 5 4 3 2 1 0
DATA[15:0]
R/W-0h
Table 7-33 OUT15_BUFFER_CODE Register Field Descriptions
Bit Field Type Reset Description
15:0 DATA[15:0] R/W 0h Code for OUT15 buffer register, unipolar straight binary format.

7.1.33 OUT0_CLEAR_CODE Register (Offset = 20h) [Reset = 0000h]

Figure 7-33 OUT0_CLEAR_CODE Register
15 14 13 12 11 10 9 8
DATA[15:0]
R/W-0h
7 6 5 4 3 2 1 0
DATA[15:0]
R/W-0h
Table 7-34 OUT0_CLEAR_CODE Register Field Descriptions
Bit Field Type Reset Description
15:0 DATA[15:0] R/W 0h Code for OUT0 clear register, unipolar straight binary format.

7.1.34 OUT1_CLEAR_CODE Register (Offset = 21h) [Reset = 0000h]

Figure 7-34 OUT1_CLEAR_CODE Register
15 14 13 12 11 10 9 8
DATA[15:0]
R/W-0h
7 6 5 4 3 2 1 0
DATA[15:0]
R/W-0h
Table 7-35 OUT1_CLEAR_CODE Register Field Descriptions
Bit Field Type Reset Description
15:0 DATA[15:0] R/W 0h Code for OUT1 clear register, unipolar straight binary format.

7.1.35 OUT2_CLEAR_CODE Register (Offset = 22h) [Reset = 0000h]

Figure 7-35 OUT2_CLEAR_CODE Register
15 14 13 12 11 10 9 8
DATA[15:0]
R/W-0h
7 6 5 4 3 2 1 0
DATA[15:0]
R/W-0h
Table 7-36 OUT2_CLEAR_CODE Register Field Descriptions
Bit Field Type Reset Description
15:0 DATA[15:0] R/W 0h Code for OUT2 clear register, unipolar straight binary format.

7.1.36 OUT3_CLEAR_CODE Register (Offset = 23h) [Reset = 0000h]

Figure 7-36 OUT3_CLEAR_CODE Register
15 14 13 12 11 10 9 8
DATA[15:0]
R/W-0h
7 6 5 4 3 2 1 0
DATA[15:0]
R/W-0h
Table 7-37 OUT3_CLEAR_CODE Register Field Descriptions
Bit Field Type Reset Description
15:0 DATA[15:0] R/W 0h Code for OUT3 clear register, unipolar straight binary format.

7.1.37 OUT4_CLEAR_CODE Register (Offset = 24h) [Reset = 0000h]

Figure 7-37 OUT4_CLEAR_CODE Register
15 14 13 12 11 10 9 8
DATA[15:0]
R/W-0h
7 6 5 4 3 2 1 0
DATA[15:0]
R/W-0h
Table 7-38 OUT4_CLEAR_CODE Register Field Descriptions
Bit Field Type Reset Description
15:0 DATA[15:0] R/W 0h Code for OUT4 clear register, unipolar straight binary format.

7.1.38 OUT5_CLEAR_CODE Register (Offset = 25h) [Reset = 0000h]

Figure 7-38 OUT5_CLEAR_CODE Register
15 14 13 12 11 10 9 8
DATA[15:0]
R/W-0h
7 6 5 4 3 2 1 0
DATA[15:0]
R/W-0h
Table 7-39 OUT5_CLEAR_CODE Register Field Descriptions
Bit Field Type Reset Description
15:0 DATA[15:0] R/W 0h Code for OUT5 clear register, unipolar straight binary format.

7.1.39 OUT6_CLEAR_CODE Register (Offset = 26h) [Reset = 0000h]

Figure 7-39 OUT6_CLEAR_CODE Register
15 14 13 12 11 10 9 8
DATA[15:0]
R/W-0h
7 6 5 4 3 2 1 0
DATA[15:0]
R/W-0h
Table 7-40 OUT6_CLEAR_CODE Register Field Descriptions
Bit Field Type Reset Description
15:0 DATA[15:0] R/W 0h Code for OUT6 clear register, unipolar straight binary format.

7.1.40 OUT7_CLEAR_CODE Register (Offset = 27h) [Reset = 0000h]

Figure 7-40 OUT7_CLEAR_CODE Register
15 14 13 12 11 10 9 8
DATA[15:0]
R/W-0h
7 6 5 4 3 2 1 0
DATA[15:0]
R/W-0h
Table 7-41 OUT7_CLEAR_CODE Register Field Descriptions
Bit Field Type Reset Description
15:0 DATA[15:0] R/W 0h Code for OUT7 clear register, unipolar straight binary format.

7.1.41 OUT8_CLEAR_CODE Register (Offset = 28h) [Reset = 0000h]

Figure 7-41 OUT8_CLEAR_CODE Register
15 14 13 12 11 10 9 8
DATA[15:0]
R/W-0h
7 6 5 4 3 2 1 0
DATA[15:0]
R/W-0h
Table 7-42 OUT8_CLEAR_CODE Register Field Descriptions
Bit Field Type Reset Description
15:0 DATA[15:0] R/W 0h Code for OUT8 clear register, unipolar straight binary format.

7.1.42 OUT9_CLEAR_CODE Register (Offset = 29h) [Reset = 0000h]

Figure 7-42 OUT9_CLEAR_CODE Register
15 14 13 12 11 10 9 8
DATA[15:0]
R/W-0h
7 6 5 4 3 2 1 0
DATA[15:0]
R/W-0h
Table 7-43 OUT9_CLEAR_CODE Register Field Descriptions
Bit Field Type Reset Description
15:0 DATA[15:0] R/W 0h Code for OUT9 clear register, unipolar straight binary format.

7.1.43 OUT10_CLEAR_CODE Register (Offset = 2Ah) [Reset = 0000h]

Figure 7-43 OUT10_CLEAR_CODE Register
15 14 13 12 11 10 9 8
DATA[15:0]
R/W-0h
7 6 5 4 3 2 1 0
DATA[15:0]
R/W-0h
Table 7-44 OUT10_CLEAR_CODE Register Field Descriptions
Bit Field Type Reset Description
15:0 DATA[15:0] R/W 0h Code for OUT10 clear register, unipolar straight binary format.

7.1.44 OUT11_CLEAR_CODE Register (Offset = 2Bh) [Reset = 0000h]

Figure 7-44 OUT11_CLEAR_CODE Register
15 14 13 12 11 10 9 8
DATA[15:0]
R/W-0h
7 6 5 4 3 2 1 0
DATA[15:0]
R/W-0h
Table 7-45 OUT11_CLEAR_CODE Register Field Descriptions
Bit Field Type Reset Description
15:0 DATA[15:0] R/W 0h Code for OUT11 clear register, unipolar straight binary format.

7.1.45 OUT12_CLEAR_CODE Register (Offset = 2Ch) [Reset = 0000h]

Figure 7-45 OUT12_CLEAR_CODE Register
15 14 13 12 11 10 9 8
DATA[15:0]
R/W-0h
7 6 5 4 3 2 1 0
DATA[15:0]
R/W-0h
Table 7-46 OUT12_CLEAR_CODE Register Field Descriptions
Bit Field Type Reset Description
15:0 DATA[15:0] R/W 0h Code for OUT12 clear register, unipolar straight binary format.

7.1.46 OUT13_CLEAR_CODE Register (Offset = 2Dh) [Reset = 0000h]

Figure 7-46 OUT13_CLEAR_CODE Register
15 14 13 12 11 10 9 8
DATA[15:0]
R/W-0h
7 6 5 4 3 2 1 0
DATA[15:0]
R/W-0h
Table 7-47 OUT13_CLEAR_CODE Register Field Descriptions
Bit Field Type Reset Description
15:0 DATA[15:0] R/W 0h Code for OUT13 clear register, unipolar straight binary format.

7.1.47 OUT14_CLEAR_CODE Register (Offset = 2Eh) [Reset = 0000h]

Figure 7-47 OUT14_CLEAR_CODE Register
15 14 13 12 11 10 9 8
DATA[15:0]
R/W-0h
7 6 5 4 3 2 1 0
DATA[15:0]
R/W-0h
Table 7-48 OUT14_CLEAR_CODE Register Field Descriptions
Bit Field Type Reset Description
15:0 DATA[15:0] R/W 0h Code for OUT14 clear register, unipolar straight binary format.

7.1.48 OUT15_CLEAR_CODE Register (Offset = 2Fh) [Reset = 0000h]

Figure 7-48 OUT15_CLEAR_CODE Register
15 14 13 12 11 10 9 8
DATA[15:0]
R/W-0h
7 6 5 4 3 2 1 0
DATA[15:0]
R/W-0h
Table 7-49 OUT15_CLEAR_CODE Register Field Descriptions
Bit Field Type Reset Description
15:0 DATA[15:0] R/W 0h Code for OUT15 clear register, unipolar straight binary format.

7.1.49 GPIO_DATA Register (Offset = 31h) [Reset = 0001h]

Figure 7-49 GPIO_DATA Register
15 14 13 12 11 10 9 8
RESERVED
R-0h
7 6 5 4 3 2 1 0
RESERVED GPIO
R-0h R/W-1h
Table 7-50 GPIO_DATA Register Field Descriptions
Bit Field Type Reset Description
15:1 RESERVED R 0h
0 GPIO R/W 1h GPIO bit.
For write operation, the GPIO pin operates as an output. Write a 1 to set the corresponding GPIO pin to either high impedance (FLEXIO_OUT_ODE=1) or logic 1 (FLEXIO_OUT_ODE=0). Write a 0 to set the corresponding GPIO pin to logic low. For read operations the GPIO pin operates as an input. Read to receive the status of the corresponding GPIO pin, which is determined by the voltage at the pin; the bit reads as 0 at start-up if the voltage at this pin is less than VIH (the register value, 1 by default, is not returned on read). After a reset event, the GPIO pin is in a high-impedance state.

7.1.50 DAC_STATUS Register (Offset = 32h) [Reset = 0000h]

Figure 7-50 DAC_STATUS Register
15 14 13 12 11 10 9 8
OUT15_
SC_STS		 OUT14_
SC_STS		 OUT13_
SC_STS		 OUT12_
SC_STS		 OUT11_
SC_STS		 OUT10_
SC_STS		 OUT9_
SC_STS		 OUT8_
SC_STS
R-0h R-0h R-0h R-0h R-0h R-0h R-0h R-0h
7 6 5 4 3 2 1 0
OUT7_
SC_STS		 OUT6_
SC_STS		 OUT5_
SC_STS		 OUT4_
SC_STS		 OUT3_
SC_STS		 OUT2_
SC_STS		 OUT1_
SC_STS		 OUT0_
SC_STS
R-0h R-0h R-0h R-0h R-0h R-0h R-0h R-0h
Table 7-51 DAC_STATUS Register Field Descriptions
Bit Field Type Reset Description
15 OUT15_SC_STS R 0h DAC short circuit condition, indicating whether this DAC channel is shorted to ground.
0h = DAC channel is not in short circuit condition
1h = DAC channel is in short circuit condition
14 OUT14_SC_STS R 0h DAC short circuit condition, indicating whether this DAC channel is shorted to ground.
0h = DAC channel is not in short circuit condition
1h = DAC channel is in short circuit condition
13 OUT13_SC_STS R 0h DAC short circuit condition, indicating whether this DAC channel is shorted to ground.
0h = DAC channel is not in short circuit condition
1h = DAC channel is in short circuit condition
12 OUT12_SC_STS R 0h DAC short circuit condition, indicating whether this DAC channel is shorted to ground.
0h = DAC channel is not in short circuit condition
1h = DAC channel is in short circuit condition
11 OUT11_SC_STS R 0h DAC short circuit condition, indicating whether this DAC channel is shorted to ground.
0h = DAC channel is not in short circuit condition
1h = DAC channel is in short circuit condition
10 OUT10_SC_STS R 0h DAC short circuit condition, indicating whether this DAC channel is shorted to ground.
0h = DAC channel is not in short circuit condition
1h = DAC channel is in short circuit condition
9 OUT9_SC_STS R 0h DAC short circuit condition, indicating whether this DAC channel is shorted to ground.
0h = DAC channel is not in short circuit condition
1h = DAC channel is in short circuit condition
8 OUT8_SC_STS R 0h DAC short circuit condition, indicating whether this DAC channel is shorted to ground.
0h = DAC channel is not in short circuit condition
1h = DAC channel is in short circuit condition
7 OUT7_SC_STS R 0h DAC short circuit condition, indicating whether this DAC channel is shorted to ground.
0h = DAC channel is not in short circuit condition
1h = DAC channel is in short circuit condition
6 OUT6_SC_STS R 0h DAC short circuit condition, indicating whether this DAC channel is shorted to ground.
0h = DAC channel is not in short circuit condition
1h = DAC channel is in short circuit condition
5 OUT5_SC_STS R 0h DAC short circuit condition, indicating whether this DAC channel is shorted to ground.
0h = DAC channel is not in short circuit condition
1h = DAC channel is in short circuit condition
4 OUT4_SC_STS R 0h DAC short circuit condition, indicating whether this DAC channel is shorted to ground.
0h = DAC channel is not in short circuit condition
1h = DAC channel is in short circuit condition
3 OUT3_SC_STS R 0h DAC short circuit condition, indicating whether this DAC channel is shorted to ground.
0h = DAC channel is not in short circuit condition
1h = DAC channel is in short circuit condition
2 OUT2_SC_STS R 0h DAC short circuit condition, indicating whether this DAC channel is shorted to ground.
0h = DAC channel is not in short circuit condition
1h = DAC channel is in short circuit condition
1 OUT1_SC_STS R 0h DAC short circuit condition, indicating whether this DAC channel is shorted to ground.
0h = DAC channel is not in short circuit condition
1h = DAC channel is in short circuit condition
0 OUT0_SC_STS R 0h DAC short circuit condition, indicating whether this DAC channel is shorted to ground.
0h = DAC channel is not in short circuit condition
1h = DAC channel is in short circuit condition